[llvm] r284406 - GlobalISel: support wider range of load/store sizes in AArch64.
Tim Northover via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 17 11:36:53 PDT 2016
Author: tnorthover
Date: Mon Oct 17 13:36:53 2016
New Revision: 284406
URL: http://llvm.org/viewvc/llvm-project?rev=284406&view=rev
Log:
GlobalISel: support wider range of load/store sizes in AArch64.
Modified:
llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp?rev=284406&r1=284405&r2=284406&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp Mon Oct 17 13:36:53 2016
@@ -222,6 +222,10 @@ static unsigned selectLoadStoreUIOp(unsi
switch (RegBankID) {
case AArch64::GPRRegBankID:
switch (OpSize) {
+ case 8:
+ return isStore ? AArch64::STRBBui : AArch64::LDRBBui;
+ case 16:
+ return isStore ? AArch64::STRHHui : AArch64::LDRHHui;
case 32:
return isStore ? AArch64::STRWui : AArch64::LDRWui;
case 64:
@@ -229,6 +233,10 @@ static unsigned selectLoadStoreUIOp(unsi
}
case AArch64::FPRRegBankID:
switch (OpSize) {
+ case 8:
+ return isStore ? AArch64::STRBui : AArch64::LDRBui;
+ case 16:
+ return isStore ? AArch64::STRHui : AArch64::LDRHui;
case 32:
return isStore ? AArch64::STRSui : AArch64::LDRSui;
case 64:
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir?rev=284406&r1=284405&r2=284406&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir Mon Oct 17 13:36:53 2016
@@ -79,11 +79,17 @@
define void @load_s64_gpr(i64* %addr) { ret void }
define void @load_s32_gpr(i32* %addr) { ret void }
+ define void @load_s16_gpr(i16* %addr) { ret void }
+ define void @load_s8_gpr(i8* %addr) { ret void }
define void @load_s64_fpr(i64* %addr) { ret void }
define void @load_s32_fpr(i32* %addr) { ret void }
+ define void @load_s16_fpr(i16* %addr) { ret void }
+ define void @load_s8_fpr(i8* %addr) { ret void }
define void @store_s64_gpr(i64* %addr) { ret void }
define void @store_s32_gpr(i32* %addr) { ret void }
+ define void @store_s16_gpr(i16* %addr) { ret void }
+ define void @store_s8_gpr(i8* %addr) { ret void }
define void @store_s64_fpr(i64* %addr) { ret void }
define void @store_s32_fpr(i32* %addr) { ret void }
@@ -1496,6 +1502,56 @@ body: |
...
---
+# CHECK-LABEL: name: load_s16_gpr
+name: load_s16_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr64sp }
+# CHECK-NEXT: - { id: 1, class: gpr32 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %x0
+# CHECK: %1 = LDRHHui %0, 0 :: (load 2 from %ir.addr)
+body: |
+ bb.0:
+ liveins: %x0
+
+ %0(p0) = COPY %x0
+ %1(s16) = G_LOAD %0 :: (load 2 from %ir.addr)
+
+...
+
+---
+# CHECK-LABEL: name: load_s8_gpr
+name: load_s8_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr64sp }
+# CHECK-NEXT: - { id: 1, class: gpr32 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %x0
+# CHECK: %1 = LDRBBui %0, 0 :: (load 1 from %ir.addr)
+body: |
+ bb.0:
+ liveins: %x0
+
+ %0(p0) = COPY %x0
+ %1(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
+
+...
+
+---
# CHECK-LABEL: name: load_s64_fpr
name: load_s64_fpr
legalized: true
@@ -1546,6 +1602,56 @@ body: |
...
---
+# CHECK-LABEL: name: load_s16_fpr
+name: load_s16_fpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr64sp }
+# CHECK-NEXT: - { id: 1, class: fpr16 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: fpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %x0
+# CHECK: %1 = LDRHui %0, 0 :: (load 2 from %ir.addr)
+body: |
+ bb.0:
+ liveins: %x0
+
+ %0(p0) = COPY %x0
+ %1(s16) = G_LOAD %0 :: (load 2 from %ir.addr)
+
+...
+
+---
+# CHECK-LABEL: name: load_s8_fpr
+name: load_s8_fpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr64sp }
+# CHECK-NEXT: - { id: 1, class: fpr8 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: fpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %x0
+# CHECK: %1 = LDRBui %0, 0 :: (load 1 from %ir.addr)
+body: |
+ bb.0:
+ liveins: %x0
+
+ %0(p0) = COPY %x0
+ %1(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
+
+...
+
+---
# CHECK-LABEL: name: store_s64_gpr
name: store_s64_gpr
legalized: true
@@ -1599,6 +1705,60 @@ body: |
...
+---
+# CHECK-LABEL: name: store_s16_gpr
+name: store_s16_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr64sp }
+# CHECK-NEXT: - { id: 1, class: gpr32 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %x0
+# CHECK: %1 = COPY %w1
+# CHECK: STRHHui %1, %0, 0 :: (store 2 into %ir.addr)
+body: |
+ bb.0:
+ liveins: %x0, %w1
+
+ %0(p0) = COPY %x0
+ %1(s16) = COPY %w1
+ G_STORE %1, %0 :: (store 2 into %ir.addr)
+
+...
+
+---
+# CHECK-LABEL: name: store_s8_gpr
+name: store_s8_gpr
+legalized: true
+regBankSelected: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr64sp }
+# CHECK-NEXT: - { id: 1, class: gpr32 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %x0
+# CHECK: %1 = COPY %w1
+# CHECK: STRBBui %1, %0, 0 :: (store 1 into %ir.addr)
+body: |
+ bb.0:
+ liveins: %x0, %w1
+
+ %0(p0) = COPY %x0
+ %1(s8) = COPY %w1
+ G_STORE %1, %0 :: (store 1 into %ir.addr)
+
+...
+
---
# CHECK-LABEL: name: store_s64_fpr
name: store_s64_fpr
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