[llvm] r284268 - [DAG] avoid creating illegal node when transforming negated shifted sign bit

[Sanjay Patel via llvm-commits]

Author: spatel
Date: Fri Oct 14 14:46:31 2016
New Revision: 284268

URL: http://llvm.org/viewvc/llvm-project?rev=284268&view=rev
Log:
[DAG] avoid creating illegal node when transforming negated shifted sign bit

Eli noted this potential bug in the post-commit thread for:
https://reviews.llvm.org/rL284239
...but I'm not sure how to trigger it, so there's no test case yet.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=284268&r1=284267&r2=284268&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Oct 14 14:46:31 2016
@@ -1962,8 +1962,9 @@ SDValue DAGCombiner::visitSUB(SDNode *N)
       (N1->getOpcode() == ISD::SRA || N1->getOpcode() == ISD::SRL)) {
     ConstantSDNode *ShiftAmt = isConstOrConstSplat(N1.getOperand(1));
     if (ShiftAmt && ShiftAmt->getZExtValue() == VT.getScalarSizeInBits() - 1) {
-      auto NewOpcode = N1->getOpcode() == ISD::SRA ? ISD::SRL :ISD::SRA;
-      return DAG.getNode(NewOpcode, DL, VT, N1.getOperand(0), N1.getOperand(1));
+      auto NewOpc = N1->getOpcode() == ISD::SRA ? ISD::SRL :ISD::SRA;
+      if (!LegalOperations || TLI.isOperationLegal(NewOpc, VT))
+        return DAG.getNode(NewOpc, DL, VT, N1.getOperand(0), N1.getOperand(1));
     }
   }