[PATCH] D25500: AMDGPU: Workaround for instruction size with literals

[Matt Arsenault via llvm-commits]

arsenm updated this revision to Diff 74707.
arsenm added a comment.

Attach right patch


https://reviews.llvm.org/D25500

Files:
  lib/Target/AMDGPU/SIInstrInfo.cpp


Index: lib/Target/AMDGPU/SIInstrInfo.cpp
===================================================================
--- lib/Target/AMDGPU/SIInstrInfo.cpp
+++ lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -3449,7 +3449,10 @@
 
   // If we have a definitive size, we can use it. Otherwise we need to inspect
   // the operands to know the size.
-  if (DescSize != 0)
+  //
+  // FIXME: Instructions that have a base 32-bit encoding report their size as
+  // 4, even though they are really 8 bytes if they have a literal operand.
+  if (DescSize != 0 && DescSize != 4)
     return DescSize;
 
   // 4-byte instructions may have a 32-bit literal encoded after them. Check
@@ -3472,6 +3475,9 @@
     return 4;
   }
 
+  if (DescSize == 4)
+    return 4;
+
   switch (Opc) {
   case TargetOpcode::IMPLICIT_DEF:
   case TargetOpcode::KILL:


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