Buildbot troubles? (Re: [llvm] r284215 - AMDGPU: Fix use-after-frees)

[Nicolai Hähnle via llvm-commits]

There's a build bot failure which points at this commit, but since the 
failure and bot have nothing to do with AMDGPU, I'm going to assume that 
it's a false positive and something is wrong with the bot.

See here: 
http://lab.llvm.org:8011/builders/clang-ppc64be-linux-multistage/builds/5311

On 14.10.2016 11:03, Nicolai Haehnle via llvm-commits wrote:
> Author: nha
> Date: Fri Oct 14 04:03:04 2016
> New Revision: 284215
>
> URL: http://llvm.org/viewvc/llvm-project?rev=284215&view=rev
> Log:
> AMDGPU: Fix use-after-frees
>
> Reviewers: arsenm, tstellarAMD
>
> Subscribers: kzhuravl, wdng, yaxunl, tony-tye, llvm-commits
>
> Differential Revision: https://reviews.llvm.org/D25312
>
> Modified:
>     llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
>     llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp
>
> Modified: llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp?rev=284215&r1=284214&r2=284215&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp Fri Oct 14 04:03:04 2016
> @@ -1274,8 +1274,6 @@ static MachineBasicBlock::iterator loadM
>    BuildMI(*RemainderBB, First, DL, TII->get(AMDGPU::S_MOV_B64), AMDGPU::EXEC)
>      .addReg(SaveExec);
>
> -  MI.eraseFromParent();
> -
>    return InsPt;
>  }
>
> @@ -1362,14 +1360,14 @@ static MachineBasicBlock *emitIndirectSr
>    MachineRegisterInfo &MRI = MF->getRegInfo();
>
>    unsigned Dst = MI.getOperand(0).getReg();
> -  const MachineOperand *SrcVec = TII->getNamedOperand(MI, AMDGPU::OpName::src);
> +  unsigned SrcReg = TII->getNamedOperand(MI, AMDGPU::OpName::src)->getReg();
>    int Offset = TII->getNamedOperand(MI, AMDGPU::OpName::offset)->getImm();
>
> -  const TargetRegisterClass *VecRC = MRI.getRegClass(SrcVec->getReg());
> +  const TargetRegisterClass *VecRC = MRI.getRegClass(SrcReg);
>
>    unsigned SubReg;
>    std::tie(SubReg, Offset)
> -    = computeIndirectRegAndOffset(TRI, VecRC, SrcVec->getReg(), Offset);
> +    = computeIndirectRegAndOffset(TRI, VecRC, SrcReg, Offset);
>
>    bool UseGPRIdxMode = ST.hasVGPRIndexMode() && EnableVGPRIndexMode;
>
> @@ -1382,14 +1380,14 @@ static MachineBasicBlock *emitIndirectSr
>        // to avoid interfering with other uses, so probably requires a new
>        // optimization pass.
>        BuildMI(MBB, I, DL, TII->get(AMDGPU::V_MOV_B32_e32), Dst)
> -        .addReg(SrcVec->getReg(), RegState::Undef, SubReg)
> -        .addReg(SrcVec->getReg(), RegState::Implicit)
> +        .addReg(SrcReg, RegState::Undef, SubReg)
> +        .addReg(SrcReg, RegState::Implicit)
>          .addReg(AMDGPU::M0, RegState::Implicit);
>        BuildMI(MBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_OFF));
>      } else {
>        BuildMI(MBB, I, DL, TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst)
> -        .addReg(SrcVec->getReg(), RegState::Undef, SubReg)
> -        .addReg(SrcVec->getReg(), RegState::Implicit);
> +        .addReg(SrcReg, RegState::Undef, SubReg)
> +        .addReg(SrcReg, RegState::Implicit);
>      }
>
>      MI.eraseFromParent();
> @@ -1412,7 +1410,6 @@ static MachineBasicBlock *emitIndirectSr
>        .addImm(VGPRIndexMode::SRC0_ENABLE);
>      SetOn->getOperand(3).setIsUndef();
>
> -
>      // Disable again after the loop.
>      BuildMI(MBB, std::next(I), DL, TII->get(AMDGPU::S_SET_GPR_IDX_OFF));
>    }
> @@ -1422,15 +1419,17 @@ static MachineBasicBlock *emitIndirectSr
>
>    if (UseGPRIdxMode) {
>      BuildMI(*LoopBB, InsPt, DL, TII->get(AMDGPU::V_MOV_B32_e32), Dst)
> -      .addReg(SrcVec->getReg(), RegState::Undef, SubReg)
> -      .addReg(SrcVec->getReg(), RegState::Implicit)
> +      .addReg(SrcReg, RegState::Undef, SubReg)
> +      .addReg(SrcReg, RegState::Implicit)
>        .addReg(AMDGPU::M0, RegState::Implicit);
>    } else {
>      BuildMI(*LoopBB, InsPt, DL, TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst)
> -      .addReg(SrcVec->getReg(), RegState::Undef, SubReg)
> -      .addReg(SrcVec->getReg(), RegState::Implicit);
> +      .addReg(SrcReg, RegState::Undef, SubReg)
> +      .addReg(SrcReg, RegState::Implicit);
>    }
>
> +  MI.eraseFromParent();
> +
>    return LoopBB;
>  }
>
> @@ -1554,6 +1553,8 @@ static MachineBasicBlock *emitIndirectDs
>      MovRel->tieOperands(ImpDefIdx, ImpUseIdx);
>    }
>
> +  MI.eraseFromParent();
> +
>    return LoopBB;
>  }
>
>
> Modified: llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp?rev=284215&r1=284214&r2=284215&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp (original)
> +++ llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp Fri Oct 14 04:03:04 2016
> @@ -611,8 +611,8 @@ void SIRegisterInfo::eliminateFrameIndex
>              TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)->getReg(),
>              FrameInfo.getObjectOffset(Index) +
>              TII->getNamedOperand(*MI, AMDGPU::OpName::offset)->getImm(), RS);
> -      MI->eraseFromParent();
>        MFI->addToSpilledVGPRs(getNumSubRegsForSpillOp(MI->getOpcode()));
> +      MI->eraseFromParent();
>        break;
>      case AMDGPU::SI_SPILL_V32_RESTORE:
>      case AMDGPU::SI_SPILL_V64_RESTORE:
>
>
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