[PATCH] D25318: [DAG] Don't increase SDNodeOrder for dbg.value/declare.

[Mikael Holmén via llvm-commits]

uabelho added a comment.

In https://reviews.llvm.org/D25318#569595, @MatzeB wrote:

> Yes the presence or absence of DbgValues should not affect the generated (assembly) code.
>
> Do you have any idea why numbering the DbgValues affects the schedule? At a first glance I only found the node order used in comparisons and sorting which shouldn't be affected whether you count the DbgValues or not.


What I saw when I debugged this in my out-of-tree target was that in ScheduleDAGRRList.cpp, the IROrder is used e.g via bu_ls_rr_sort::operator() (via BURRSort, via SPQ->getNodeOrdering), affecting the order in which the instructions were placed in the final schedule, which in turn affected register allocation.

Turning on -debug printouts when compiling the example in the patch you can see that the result of the scheduler is different when the dbg.value is present.


https://reviews.llvm.org/D25318