[PATCH] D25202: LegalizeDAG: Implement PROMOTE for ISD::BITREVERSE

[Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL284163: LegalizeDAG: Implement PROMOTE for ISD::BITREVERSE (authored by tstellar).

Changed prior to commit:
  https://reviews.llvm.org/D25202?vs=73308&id=74584#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D25202

Files:
  llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp


Index: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -4084,10 +4084,11 @@
     }
     Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
     break;
+  case ISD::BITREVERSE:
   case ISD::BSWAP: {
     unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
     Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
-    Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
+    Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
     Tmp1 = DAG.getNode(
         ISD::SRL, dl, NVT, Tmp1,
         DAG.getConstant(DiffBits, dl,


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