[llvm] r284146 - [AArch64][RegisterBankInfo] Switch to fully static opds mapping for G_BITCAST.

[Quentin Colombet via llvm-commits]

Author: qcolombet
Date: Thu Oct 13 13:46:38 2016
New Revision: 284146

URL: http://llvm.org/viewvc/llvm-project?rev=284146&view=rev
Log:
[AArch64][RegisterBankInfo] Switch to fully static opds mapping for G_BITCAST.

NFC.

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp

Modified: llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp?rev=284146&r1=284145&r2=284146&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp Thu Oct 13 13:46:38 2016
@@ -477,10 +477,16 @@ AArch64RegisterBankInfo::getInstrMapping
   case TargetOpcode::G_BITCAST: {
     LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
     LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());
-    // If we are on the same bank, we can use the "same kind" mapping.
-    if (DstTy.isVector() == SrcTy.isVector())
-      return getSameKindOfOperandsMapping(MI);
-    break;
+    unsigned Size = DstTy.getSizeInBits();
+    bool DstIsGPR = !DstTy.isVector();
+    bool SrcIsGPR = !SrcTy.isVector();
+    const RegisterBank &DstRB =
+        DstIsGPR ? AArch64::GPRRegBank : AArch64::FPRRegBank;
+    const RegisterBank &SrcRB =
+        SrcIsGPR ? AArch64::GPRRegBank : AArch64::FPRRegBank;
+    return InstructionMapping{DefaultMappingID, copyCost(DstRB, SrcRB, Size),
+                              AArch64::getCopyMapping(DstIsGPR, SrcIsGPR, Size),
+                              /*NumOperands*/ 2};
   }
   default:
     break;