[PATCH] D23446: [X86] Enable setcc to srl(ctlz) transformation on btver2 architectures.

[Sanjay Patel via llvm-commits]

spatel added inline comments.


================
Comment at: lib/Target/X86/X86ISelLowering.cpp:29037-29042
+  // Check the OR user is a zero extend and that it is extending to 32-bit or
+  // more. The code generated by srl(ctlz) for 16-bit or less variants of the
+  // pattern would require extra instructions to clear the upper bits.
+  if (!N->hasOneUse() || !(N->use_begin()->getOpcode() == ISD::ZERO_EXTEND) ||
+      !N->use_begin()->getSimpleValueType(0).bitsGE(MVT::i32))
+    return SDValue();
----------------
The pattern must always begin with zext. Is there some reason not to start in combineZext() rather than combineOr()?


https://reviews.llvm.org/D23446