[llvm] r284117 - [DAGCombiner] Add vector support to C2-(A+C1) -> (C2-C1)-A folding

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Thu Oct 13 07:49:31 2016
New Revision: 284117

URL: http://llvm.org/viewvc/llvm-project?rev=284117&view=rev
Log:
[DAGCombiner] Add vector support to C2-(A+C1) -> (C2-C1)-A folding

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/test/CodeGen/X86/combine-sub.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=284117&r1=284116&r2=284117&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Oct 13 07:49:31 2016
@@ -1939,7 +1939,6 @@ SDValue DAGCombiner::visitSUB(SDNode *N)
                                       N1.getNode());
   }
 
-  ConstantSDNode *N0C = getAsNonOpaqueConstant(N0);
   ConstantSDNode *N1C = getAsNonOpaqueConstant(N1);
 
   // fold (sub x, c) -> (add x, -c)
@@ -1965,10 +1964,11 @@ SDValue DAGCombiner::visitSUB(SDNode *N)
     return N0.getOperand(0);
 
   // fold C2-(A+C1) -> (C2-C1)-A
-  if (N1.getOpcode() == ISD::ADD && N0C) {
-    if (auto *N1C1 = dyn_cast<ConstantSDNode>(N1.getOperand(1).getNode())) {
-      SDValue NewC =
-          DAG.getConstant(N0C->getAPIntValue() - N1C1->getAPIntValue(), DL, VT);
+  if (N1.getOpcode() == ISD::ADD) {
+    SDValue N11 = N1.getOperand(1);
+    if (isConstantOrConstantVector(N0, /* NoOpaques */ true) &&
+        isConstantOrConstantVector(N11, /* NoOpaques */ true)) {
+      SDValue NewC = DAG.getNode(ISD::SUB, DL, VT, N0, N11);
       return DAG.getNode(ISD::SUB, DL, VT, NewC, N1.getOperand(0));
     }
   }

Modified: llvm/trunk/test/CodeGen/X86/combine-sub.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-sub.ll?rev=284117&r1=284116&r2=284117&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/combine-sub.ll (original)
+++ llvm/trunk/test/CodeGen/X86/combine-sub.ll Thu Oct 13 07:49:31 2016
@@ -112,16 +112,14 @@ define <4 x i32> @combine_vec_sub_add1(<
 define <4 x i32> @combine_vec_sub_constant_add(<4 x i32> %a) {
 ; SSE-LABEL: combine_vec_sub_constant_add:
 ; SSE:       # BB#0:
-; SSE-NEXT:    paddd {{.*}}(%rip), %xmm0
-; SSE-NEXT:    movdqa {{.*#+}} xmm1 = [3,2,1,0]
+; SSE-NEXT:    movdqa {{.*#+}} xmm1 = [3,1,4294967295,4294967293]
 ; SSE-NEXT:    psubd %xmm0, %xmm1
 ; SSE-NEXT:    movdqa %xmm1, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: combine_vec_sub_constant_add:
 ; AVX:       # BB#0:
-; AVX-NEXT:    vpaddd {{.*}}(%rip), %xmm0, %xmm0
-; AVX-NEXT:    vmovdqa {{.*#+}} xmm1 = [3,2,1,0]
+; AVX-NEXT:    vmovdqa {{.*#+}} xmm1 = [3,1,4294967295,4294967293]
 ; AVX-NEXT:    vpsubd %xmm0, %xmm1, %xmm0
 ; AVX-NEXT:    retq
   %1 = add <4 x i32> %a, <i32 0, i32 1, i32 2, i32 3>