[llvm] r284113 - [DAGCombiner] Add vector support to (sub -1, x) -> (xor x, -1) canonicalization
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 13 05:05:20 PDT 2016
Author: rksimon
Date: Thu Oct 13 07:05:20 2016
New Revision: 284113
URL: http://llvm.org/viewvc/llvm-project?rev=284113&view=rev
Log:
[DAGCombiner] Add vector support to (sub -1, x) -> (xor x, -1) canonicalization
Improves commutation potential
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/trunk/test/CodeGen/X86/combine-sub.ll
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=284113&r1=284112&r2=284113&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Oct 13 07:05:20 2016
@@ -863,6 +863,17 @@ static bool isOneConstantOrOneSplatConst
return false;
}
+// Determines if it is a constant integer of all ones or a splatted vector of a
+// constant integer of all ones (with no undefs).
+// Do not permit build vector implicit truncation.
+static bool isAllOnesConstantOrAllOnesSplatConstant(SDValue N) {
+ unsigned BitWidth = N.getScalarValueSizeInBits();
+ if (ConstantSDNode *Splat = isConstOrConstSplat(N))
+ return Splat->isAllOnesValue() &&
+ Splat->getAPIntValue().getBitWidth() == BitWidth;
+ return false;
+}
+
SDValue DAGCombiner::ReassociateOps(unsigned Opc, const SDLoc &DL, SDValue N0,
SDValue N1) {
EVT VT = N0.getValueType();
@@ -1938,7 +1949,7 @@ SDValue DAGCombiner::visitSUB(SDNode *N)
}
// Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1)
- if (isAllOnesConstant(N0))
+ if (isAllOnesConstantOrAllOnesSplatConstant(N0))
return DAG.getNode(ISD::XOR, DL, VT, N1, N0);
// fold A-(A-B) -> B
Modified: llvm/trunk/test/CodeGen/X86/combine-sub.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-sub.ll?rev=284113&r1=284112&r2=284113&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/combine-sub.ll (original)
+++ llvm/trunk/test/CodeGen/X86/combine-sub.ll Thu Oct 13 07:05:20 2016
@@ -50,14 +50,13 @@ define <4 x i32> @combine_vec_sub_negone
; SSE-LABEL: combine_vec_sub_negone:
; SSE: # BB#0:
; SSE-NEXT: pcmpeqd %xmm1, %xmm1
-; SSE-NEXT: psubd %xmm0, %xmm1
-; SSE-NEXT: movdqa %xmm1, %xmm0
+; SSE-NEXT: pxor %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_sub_negone:
; AVX: # BB#0:
; AVX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
-; AVX-NEXT: vpsubd %xmm0, %xmm1, %xmm0
+; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq
%1 = sub <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, %x
ret <4 x i32> %1
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