[llvm] r284071 - GlobalISel: select G_BRCOND instructions on AArch64.

[Tim Northover via llvm-commits]

Author: tnorthover
Date: Wed Oct 12 17:49:01 2016
New Revision: 284071

URL: http://llvm.org/viewvc/llvm-project?rev=284071&view=rev
Log:
GlobalISel: select G_BRCOND instructions on AArch64.

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir

Modified: llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp?rev=284071&r1=284070&r2=284071&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp Wed Oct 12 17:49:01 2016
@@ -299,6 +299,28 @@ bool AArch64InstructionSelector::select(
     return true;
   }
 
+  case TargetOpcode::G_BRCOND: {
+    if (Ty.getSizeInBits() > 32) {
+      // We shouldn't need this on AArch64, but it would be implemented as an
+      // EXTRACT_SUBREG followed by a TBNZW because TBNZX has no encoding if the
+      // bit being tested is < 32.
+      DEBUG(dbgs() << "G_BRCOND has type: " << Ty
+                   << ", expected at most 32-bits");
+      return false;
+    }
+
+    const unsigned CondReg = I.getOperand(0).getReg();
+    MachineBasicBlock *DestMBB = I.getOperand(1).getMBB();
+
+    auto MIB = BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::TBNZW))
+                   .addUse(CondReg)
+                   .addImm(/*bit offset=*/0)
+                   .addMBB(DestMBB);
+
+    I.eraseFromParent();
+    return constrainSelectedInstRegOperands(*MIB.getInstr(), TII, TRI, RBI);
+  }
+
   case TargetOpcode::G_CONSTANT: {
     if (Ty.getSizeInBits() <= 32)
       I.setDesc(TII.get(AArch64::MOVi32imm));

Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir?rev=284071&r1=284070&r2=284071&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir Wed Oct 12 17:49:01 2016
@@ -54,6 +54,7 @@
   define void @fdiv_s64_gpr() { ret void }
 
   define void @unconditional_br() { ret void }
+  define void @conditional_br() { ret void }
 
   define void @load_s64_gpr(i64* %addr) { ret void }
   define void @load_s32_gpr(i32* %addr) { ret void }
@@ -1013,6 +1014,29 @@ body:             |
 ...
 
 ---
+# CHECK-LABEL: name: conditional_br
+name:            conditional_br
+legalized:       true
+regBankSelected: true
+
+registers:
+  - { id: 0, class: gpr }
+
+# CHECK:  body:
+# CHECK:   bb.0:
+# CHECK:    TBNZW %0, 0, %bb.1
+# CHECK:    B %bb.0
+body:             |
+  bb.0:
+    successors: %bb.0, %bb.1
+    %0(s1) = COPY %w0
+    G_BRCOND %0(s1), %bb.1
+    G_BR %bb.0
+
+  bb.1:
+...
+
+---
 # CHECK-LABEL: name: load_s64_gpr
 name:            load_s64_gpr
 legalized:       true