[llvm] r283974 - [AArch64][InstructionSelector] Fix unintended test changes in r283973.
Quentin Colombet via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 11 21:12:44 PDT 2016
Author: qcolombet
Date: Tue Oct 11 23:12:44 2016
New Revision: 283974
URL: http://llvm.org/viewvc/llvm-project?rev=283974&view=rev
Log:
[AArch64][InstructionSelector] Fix unintended test changes in r283973.
I screwed up my merge conflict and lost some of the CHECK lines.
Modified:
llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir?rev=283974&r1=283973&r2=283974&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir Tue Oct 11 23:12:44 2016
@@ -1447,15 +1447,18 @@ regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64all }
-# CHECK-NEXT: - { id: 1, class: gpr64all }
+# CHECK-NEXT: - { id: 1, class: fpr64 }
# CHECK-NEXT: - { id: 2, class: gpr64all }
# CHECK-NEXT: - { id: 3, class: gpr64all }
registers:
- { id: 0, class: gpr }
- - { id: 1, class: gpr }
+ - { id: 1, class: fpr }
- { id: 2, class: gpr }
- { id: 3, class: gpr }
- # CHECK: %2 = COPY %0
+# CHECK: body:
+# CHECK: %0 = COPY %x0
+# CHECK: %1 = COPY %0
+# CHECK: %2 = COPY %0
# CHECK: %3 = COPY %2
body: |
bb.0:
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