[PATCH] D25278: [AVR] Add AVRISelDAGToDAG.cpp
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 11 07:22:08 PDT 2016
kparzysz requested changes to this revision.
kparzysz added a comment.
This revision now requires changes to proceed.
Please use the recommended workflow for selection where applicable: selectXyz(n) functions replace n with selected code and return void. The use of selectImpl looks like a remnant of some old code.
================
Comment at: lib/Target/AVR/AVRISelDAGToDAG.cpp:112
+ if ((VT == MVT::i8 && isUInt<6>(RHSC)) ||
+ (VT == MVT::i16 && RHSC >= 0 && RHSC < 63)) {
+ Base = N.getOperand(0);
----------------
You can factor the isUInt out of this condition, e.g,:
`if (isUInt<6>(RHSC) && (VT == MVT::i8 || VT == MVT::i16))`
================
Comment at: lib/Target/AVR/AVRISelDAGToDAG.cpp:130
+ // We only care if this load uses a POSTINC or PREDEC mode.
+ if ((LD->getExtensionType() != ISD::NON_EXTLOAD) ||
+ (AM != ISD::POST_INC && AM != ISD::PRE_DEC)) {
----------------
I think it should be "== ISD::NON_EXTLOAD".
Repository:
rL LLVM
https://reviews.llvm.org/D25278
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