[llvm] r283881 - [X86][SSE] Regenerate vector load-trunc test

Simon Pilgrim via llvm-commits llvm-commits at lists.llvm.org
Tue Oct 11 06:55:50 PDT 2016


Author: rksimon
Date: Tue Oct 11 08:55:49 2016
New Revision: 283881

URL: http://llvm.org/viewvc/llvm-project?rev=283881&view=rev
Log:
[X86][SSE] Regenerate vector load-trunc test

Modified:
    llvm/trunk/test/CodeGen/X86/vec-trunc-store.ll

Modified: llvm/trunk/test/CodeGen/X86/vec-trunc-store.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec-trunc-store.ll?rev=283881&r1=283880&r2=283881&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec-trunc-store.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec-trunc-store.ll Tue Oct 11 08:55:49 2016
@@ -1,6 +1,18 @@
-; RUN: llc < %s -march=x86-64
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s
 
 define void @foo(<8 x i32>* %p) nounwind {
+; CHECK-LABEL: foo:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movdqa (%rdi), %xmm0
+; CHECK-NEXT:    movdqa 16(%rdi), %xmm1
+; CHECK-NEXT:    pslld $16, %xmm1
+; CHECK-NEXT:    psrad $16, %xmm1
+; CHECK-NEXT:    pslld $16, %xmm0
+; CHECK-NEXT:    psrad $16, %xmm0
+; CHECK-NEXT:    packssdw %xmm1, %xmm0
+; CHECK-NEXT:    movdqa %xmm0, (%rax)
+; CHECK-NEXT:    retq
   %t = load <8 x i32>, <8 x i32>* %p
   %cti69 = trunc <8 x i32> %t to <8 x i16>     ; <<8 x i16>> [#uses=1]
   store <8 x i16> %cti69, <8 x i16>* undef
@@ -8,6 +20,13 @@ define void @foo(<8 x i32>* %p) nounwind
 }
 
 define void @bar(<4 x i32>* %p) nounwind {
+; CHECK-LABEL: bar:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    pshuflw {{.*#+}} xmm0 = mem[0,2,2,3,4,5,6,7]
+; CHECK-NEXT:    pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,6,6,7]
+; CHECK-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
+; CHECK-NEXT:    movq %xmm0, (%rax)
+; CHECK-NEXT:    retq
   %t = load <4 x i32>, <4 x i32>* %p
   %cti44 = trunc <4 x i32> %t to <4 x i16>     ; <<4 x i16>> [#uses=1]
   store <4 x i16> %cti44, <4 x i16>* undef




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