[llvm] r283807 - GlobalISel: support selecting G_GEP instructions.
Tim Northover via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 10 14:49:49 PDT 2016
Author: tnorthover
Date: Mon Oct 10 16:49:49 2016
New Revision: 283807
URL: http://llvm.org/viewvc/llvm-project?rev=283807&view=rev
Log:
GlobalISel: support selecting G_GEP instructions.
They're basically just an alias for G_ADD on AArch64.
Modified:
llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp?rev=283807&r1=283806&r2=283807&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp Mon Oct 10 16:49:49 2016
@@ -130,6 +130,7 @@ static unsigned selectBinaryOp(unsigned
case TargetOpcode::G_AND:
return AArch64::ANDXrr;
case TargetOpcode::G_ADD:
+ case TargetOpcode::G_GEP:
return AArch64::ADDXrr;
case TargetOpcode::G_SUB:
return AArch64::SUBXrr;
@@ -340,7 +341,8 @@ bool AArch64InstructionSelector::select(
case TargetOpcode::G_SDIV:
case TargetOpcode::G_UDIV:
case TargetOpcode::G_ADD:
- case TargetOpcode::G_SUB: {
+ case TargetOpcode::G_SUB:
+ case TargetOpcode::G_GEP: {
// Reject the various things we don't support yet.
if (unsupportedBinOp(I, RBI, MRI, TRI))
return false;
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir?rev=283807&r1=283806&r2=283807&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir Mon Oct 10 16:49:49 2016
@@ -70,6 +70,7 @@
define i32 @const_s32() { ret i32 42 }
define i64 @const_s64() { ret i64 1234567890123 }
+ define i8* @gep(i8* %in) { ret i8* undef }
...
---
@@ -1121,3 +1122,23 @@ body: |
bb.0:
%0(s64) = G_CONSTANT 1234567890123
...
+
+---
+# CHECK-LABEL: name: gep
+name: gep
+legalized: true
+regBankSelected: true
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+ - { id: 2, class: gpr }
+
+# CHECK: body:
+# CHECK: %1 = MOVi64imm 42
+# CHECK: %2 = ADDXrr %0, %1
+body: |
+ bb.0:
+ %0(p0) = COPY %x0
+ %1(s64) = G_CONSTANT 42
+ %2(p0) = G_GEP %0, %1(s64)
+...
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