[llvm] r283758 - [X86] Prefer rotate by 1 over rotate by imm

[Zvi Rackover via llvm-commits]

Author: zvi
Date: Mon Oct 10 09:43:55 2016
New Revision: 283758

URL: http://llvm.org/viewvc/llvm-project?rev=283758&view=rev
Log:
[X86] Prefer rotate by 1 over rotate by imm

Summary:
Rotate by 1 is translated to 1 micro-op, while rotate with imm8 is translated to 2 micro-ops.

Fixes pr30644.

Reviewers: delena, igorb, craig.topper, spatel, RKSimon

Differential Revision: https://reviews.llvm.org/D25399

Modified:
    llvm/trunk/lib/Target/X86/X86InstrShiftRotate.td
    llvm/trunk/test/CodeGen/X86/rotate.ll

Modified: llvm/trunk/lib/Target/X86/X86InstrShiftRotate.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrShiftRotate.td?rev=283758&r1=283757&r2=283758&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrShiftRotate.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrShiftRotate.td Mon Oct 10 09:43:55 2016
@@ -609,19 +609,19 @@ def ROR64ri  : RIi8<0xC1, MRM1r, (outs G
 // Rotate by 1
 def ROR8r1   : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
                  "ror{b}\t$dst",
-                 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))],
+                 [(set GR8:$dst, (rotl GR8:$src1, (i8 7)))],
                  IIC_SR>;
 def ROR16r1  : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
                  "ror{w}\t$dst",
-                 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))],
+                 [(set GR16:$dst, (rotl GR16:$src1, (i8 15)))],
                  IIC_SR>, OpSize16;
 def ROR32r1  : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
                  "ror{l}\t$dst",
-                 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))],
+                 [(set GR32:$dst, (rotl GR32:$src1, (i8 31)))],
                  IIC_SR>, OpSize32;
 def ROR64r1  : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
                   "ror{q}\t$dst",
-                  [(set GR64:$dst, (rotr GR64:$src1, (i8 1)))],
+                  [(set GR64:$dst, (rotl GR64:$src1, (i8 63)))],
                   IIC_SR>;
 } // Constraints = "$src = $dst", SchedRW
 

Modified: llvm/trunk/test/CodeGen/X86/rotate.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/rotate.ll?rev=283758&r1=283757&r2=283758&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/rotate.ll (original)
+++ llvm/trunk/test/CodeGen/X86/rotate.ll Mon Oct 10 09:43:55 2016
@@ -183,7 +183,7 @@ define i64 @rotr1_64(i64 %A) nounwind {
 ;
 ; 64-LABEL: rotr1_64:
 ; 64:       # BB#0:
-; 64-NEXT:    rolq $63, %rdi
+; 64-NEXT:    rorq %rdi
 ; 64-NEXT:    movq %rdi, %rax
 ; 64-NEXT:    retq
 	%B = shl i64 %A, 63
@@ -296,12 +296,12 @@ define i32 @rotr1_32(i32 %A) nounwind {
 ; 32-LABEL: rotr1_32:
 ; 32:       # BB#0:
 ; 32-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; 32-NEXT:    roll $31, %eax
+; 32-NEXT:    rorl %eax
 ; 32-NEXT:    retl
 ;
 ; 64-LABEL: rotr1_32:
 ; 64:       # BB#0:
-; 64-NEXT:    roll $31, %edi
+; 64-NEXT:    rorl %edi
 ; 64-NEXT:    movl %edi, %eax
 ; 64-NEXT:    retq
 	%B = shl i32 %A, 31
@@ -414,12 +414,12 @@ define i16 @rotr1_16(i16 %A) nounwind {
 ; 32-LABEL: rotr1_16:
 ; 32:       # BB#0:
 ; 32-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
-; 32-NEXT:    rolw $15, %ax
+; 32-NEXT:    rorw %ax
 ; 32-NEXT:    retl
 ;
 ; 64-LABEL: rotr1_16:
 ; 64:       # BB#0:
-; 64-NEXT:    rolw $15, %di
+; 64-NEXT:    rorw %di
 ; 64-NEXT:    movl %edi, %eax
 ; 64-NEXT:    retq
 	%B = lshr i16 %A, 1
@@ -528,12 +528,12 @@ define i8 @rotr1_8(i8 %A) nounwind {
 ; 32-LABEL: rotr1_8:
 ; 32:       # BB#0:
 ; 32-NEXT:    movb {{[0-9]+}}(%esp), %al
-; 32-NEXT:    rolb $7, %al
+; 32-NEXT:    rorb %al
 ; 32-NEXT:    retl
 ;
 ; 64-LABEL: rotr1_8:
 ; 64:       # BB#0:
-; 64-NEXT:    rolb $7, %dil
+; 64-NEXT:    rorb %dil
 ; 64-NEXT:    movl %edi, %eax
 ; 64-NEXT:    retq
 	%B = lshr i8 %A, 1