[llvm] r283514 - [Hexagon] NFC Removing 'V4_' prefix from duplex instruction names.
Colin LeMahieu via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 6 17:15:07 PDT 2016
Author: colinl
Date: Thu Oct 6 19:15:07 2016
New Revision: 283514
URL: http://llvm.org/viewvc/llvm-project?rev=283514&view=rev
Log:
[Hexagon] NFC Removing 'V4_' prefix from duplex instruction names.
Modified:
llvm/trunk/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
llvm/trunk/lib/Target/Hexagon/HexagonIsetDx.td
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
Modified: llvm/trunk/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp?rev=283514&r1=283513&r2=283514&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp Thu Oct 6 19:15:07 2016
@@ -1087,244 +1087,244 @@ static DecodeStatus decodeImmext(MCInst
// These values are from HexagonGenMCCodeEmitter.inc and HexagonIsetDx.td
enum subInstBinaryValues {
- V4_SA1_addi_BITS = 0x0000,
- V4_SA1_addi_MASK = 0x1800,
- V4_SA1_addrx_BITS = 0x1800,
- V4_SA1_addrx_MASK = 0x1f00,
- V4_SA1_addsp_BITS = 0x0c00,
- V4_SA1_addsp_MASK = 0x1c00,
- V4_SA1_and1_BITS = 0x1200,
- V4_SA1_and1_MASK = 0x1f00,
- V4_SA1_clrf_BITS = 0x1a70,
- V4_SA1_clrf_MASK = 0x1e70,
- V4_SA1_clrfnew_BITS = 0x1a50,
- V4_SA1_clrfnew_MASK = 0x1e70,
- V4_SA1_clrt_BITS = 0x1a60,
- V4_SA1_clrt_MASK = 0x1e70,
- V4_SA1_clrtnew_BITS = 0x1a40,
- V4_SA1_clrtnew_MASK = 0x1e70,
- V4_SA1_cmpeqi_BITS = 0x1900,
- V4_SA1_cmpeqi_MASK = 0x1f00,
- V4_SA1_combine0i_BITS = 0x1c00,
- V4_SA1_combine0i_MASK = 0x1d18,
- V4_SA1_combine1i_BITS = 0x1c08,
- V4_SA1_combine1i_MASK = 0x1d18,
- V4_SA1_combine2i_BITS = 0x1c10,
- V4_SA1_combine2i_MASK = 0x1d18,
- V4_SA1_combine3i_BITS = 0x1c18,
- V4_SA1_combine3i_MASK = 0x1d18,
- V4_SA1_combinerz_BITS = 0x1d08,
- V4_SA1_combinerz_MASK = 0x1d08,
- V4_SA1_combinezr_BITS = 0x1d00,
- V4_SA1_combinezr_MASK = 0x1d08,
- V4_SA1_dec_BITS = 0x1300,
- V4_SA1_dec_MASK = 0x1f00,
- V4_SA1_inc_BITS = 0x1100,
- V4_SA1_inc_MASK = 0x1f00,
- V4_SA1_seti_BITS = 0x0800,
- V4_SA1_seti_MASK = 0x1c00,
- V4_SA1_setin1_BITS = 0x1a00,
- V4_SA1_setin1_MASK = 0x1e40,
- V4_SA1_sxtb_BITS = 0x1500,
- V4_SA1_sxtb_MASK = 0x1f00,
- V4_SA1_sxth_BITS = 0x1400,
- V4_SA1_sxth_MASK = 0x1f00,
- V4_SA1_tfr_BITS = 0x1000,
- V4_SA1_tfr_MASK = 0x1f00,
- V4_SA1_zxtb_BITS = 0x1700,
- V4_SA1_zxtb_MASK = 0x1f00,
- V4_SA1_zxth_BITS = 0x1600,
- V4_SA1_zxth_MASK = 0x1f00,
- V4_SL1_loadri_io_BITS = 0x0000,
- V4_SL1_loadri_io_MASK = 0x1000,
- V4_SL1_loadrub_io_BITS = 0x1000,
- V4_SL1_loadrub_io_MASK = 0x1000,
- V4_SL2_deallocframe_BITS = 0x1f00,
- V4_SL2_deallocframe_MASK = 0x1fc0,
- V4_SL2_jumpr31_BITS = 0x1fc0,
- V4_SL2_jumpr31_MASK = 0x1fc4,
- V4_SL2_jumpr31_f_BITS = 0x1fc5,
- V4_SL2_jumpr31_f_MASK = 0x1fc7,
- V4_SL2_jumpr31_fnew_BITS = 0x1fc7,
- V4_SL2_jumpr31_fnew_MASK = 0x1fc7,
- V4_SL2_jumpr31_t_BITS = 0x1fc4,
- V4_SL2_jumpr31_t_MASK = 0x1fc7,
- V4_SL2_jumpr31_tnew_BITS = 0x1fc6,
- V4_SL2_jumpr31_tnew_MASK = 0x1fc7,
- V4_SL2_loadrb_io_BITS = 0x1000,
- V4_SL2_loadrb_io_MASK = 0x1800,
- V4_SL2_loadrd_sp_BITS = 0x1e00,
- V4_SL2_loadrd_sp_MASK = 0x1f00,
- V4_SL2_loadrh_io_BITS = 0x0000,
- V4_SL2_loadrh_io_MASK = 0x1800,
- V4_SL2_loadri_sp_BITS = 0x1c00,
- V4_SL2_loadri_sp_MASK = 0x1e00,
- V4_SL2_loadruh_io_BITS = 0x0800,
- V4_SL2_loadruh_io_MASK = 0x1800,
- V4_SL2_return_BITS = 0x1f40,
- V4_SL2_return_MASK = 0x1fc4,
- V4_SL2_return_f_BITS = 0x1f45,
- V4_SL2_return_f_MASK = 0x1fc7,
- V4_SL2_return_fnew_BITS = 0x1f47,
- V4_SL2_return_fnew_MASK = 0x1fc7,
- V4_SL2_return_t_BITS = 0x1f44,
- V4_SL2_return_t_MASK = 0x1fc7,
- V4_SL2_return_tnew_BITS = 0x1f46,
- V4_SL2_return_tnew_MASK = 0x1fc7,
- V4_SS1_storeb_io_BITS = 0x1000,
- V4_SS1_storeb_io_MASK = 0x1000,
- V4_SS1_storew_io_BITS = 0x0000,
- V4_SS1_storew_io_MASK = 0x1000,
- V4_SS2_allocframe_BITS = 0x1c00,
- V4_SS2_allocframe_MASK = 0x1e00,
- V4_SS2_storebi0_BITS = 0x1200,
- V4_SS2_storebi0_MASK = 0x1f00,
- V4_SS2_storebi1_BITS = 0x1300,
- V4_SS2_storebi1_MASK = 0x1f00,
- V4_SS2_stored_sp_BITS = 0x0a00,
- V4_SS2_stored_sp_MASK = 0x1e00,
- V4_SS2_storeh_io_BITS = 0x0000,
- V4_SS2_storeh_io_MASK = 0x1800,
- V4_SS2_storew_sp_BITS = 0x0800,
- V4_SS2_storew_sp_MASK = 0x1e00,
- V4_SS2_storewi0_BITS = 0x1000,
- V4_SS2_storewi0_MASK = 0x1f00,
- V4_SS2_storewi1_BITS = 0x1100,
- V4_SS2_storewi1_MASK = 0x1f00
+ SA1_addi_BITS = 0x0000,
+ SA1_addi_MASK = 0x1800,
+ SA1_addrx_BITS = 0x1800,
+ SA1_addrx_MASK = 0x1f00,
+ SA1_addsp_BITS = 0x0c00,
+ SA1_addsp_MASK = 0x1c00,
+ SA1_and1_BITS = 0x1200,
+ SA1_and1_MASK = 0x1f00,
+ SA1_clrf_BITS = 0x1a70,
+ SA1_clrf_MASK = 0x1e70,
+ SA1_clrfnew_BITS = 0x1a50,
+ SA1_clrfnew_MASK = 0x1e70,
+ SA1_clrt_BITS = 0x1a60,
+ SA1_clrt_MASK = 0x1e70,
+ SA1_clrtnew_BITS = 0x1a40,
+ SA1_clrtnew_MASK = 0x1e70,
+ SA1_cmpeqi_BITS = 0x1900,
+ SA1_cmpeqi_MASK = 0x1f00,
+ SA1_combine0i_BITS = 0x1c00,
+ SA1_combine0i_MASK = 0x1d18,
+ SA1_combine1i_BITS = 0x1c08,
+ SA1_combine1i_MASK = 0x1d18,
+ SA1_combine2i_BITS = 0x1c10,
+ SA1_combine2i_MASK = 0x1d18,
+ SA1_combine3i_BITS = 0x1c18,
+ SA1_combine3i_MASK = 0x1d18,
+ SA1_combinerz_BITS = 0x1d08,
+ SA1_combinerz_MASK = 0x1d08,
+ SA1_combinezr_BITS = 0x1d00,
+ SA1_combinezr_MASK = 0x1d08,
+ SA1_dec_BITS = 0x1300,
+ SA1_dec_MASK = 0x1f00,
+ SA1_inc_BITS = 0x1100,
+ SA1_inc_MASK = 0x1f00,
+ SA1_seti_BITS = 0x0800,
+ SA1_seti_MASK = 0x1c00,
+ SA1_setin1_BITS = 0x1a00,
+ SA1_setin1_MASK = 0x1e40,
+ SA1_sxtb_BITS = 0x1500,
+ SA1_sxtb_MASK = 0x1f00,
+ SA1_sxth_BITS = 0x1400,
+ SA1_sxth_MASK = 0x1f00,
+ SA1_tfr_BITS = 0x1000,
+ SA1_tfr_MASK = 0x1f00,
+ SA1_zxtb_BITS = 0x1700,
+ SA1_zxtb_MASK = 0x1f00,
+ SA1_zxth_BITS = 0x1600,
+ SA1_zxth_MASK = 0x1f00,
+ SL1_loadri_io_BITS = 0x0000,
+ SL1_loadri_io_MASK = 0x1000,
+ SL1_loadrub_io_BITS = 0x1000,
+ SL1_loadrub_io_MASK = 0x1000,
+ SL2_deallocframe_BITS = 0x1f00,
+ SL2_deallocframe_MASK = 0x1fc0,
+ SL2_jumpr31_BITS = 0x1fc0,
+ SL2_jumpr31_MASK = 0x1fc4,
+ SL2_jumpr31_f_BITS = 0x1fc5,
+ SL2_jumpr31_f_MASK = 0x1fc7,
+ SL2_jumpr31_fnew_BITS = 0x1fc7,
+ SL2_jumpr31_fnew_MASK = 0x1fc7,
+ SL2_jumpr31_t_BITS = 0x1fc4,
+ SL2_jumpr31_t_MASK = 0x1fc7,
+ SL2_jumpr31_tnew_BITS = 0x1fc6,
+ SL2_jumpr31_tnew_MASK = 0x1fc7,
+ SL2_loadrb_io_BITS = 0x1000,
+ SL2_loadrb_io_MASK = 0x1800,
+ SL2_loadrd_sp_BITS = 0x1e00,
+ SL2_loadrd_sp_MASK = 0x1f00,
+ SL2_loadrh_io_BITS = 0x0000,
+ SL2_loadrh_io_MASK = 0x1800,
+ SL2_loadri_sp_BITS = 0x1c00,
+ SL2_loadri_sp_MASK = 0x1e00,
+ SL2_loadruh_io_BITS = 0x0800,
+ SL2_loadruh_io_MASK = 0x1800,
+ SL2_return_BITS = 0x1f40,
+ SL2_return_MASK = 0x1fc4,
+ SL2_return_f_BITS = 0x1f45,
+ SL2_return_f_MASK = 0x1fc7,
+ SL2_return_fnew_BITS = 0x1f47,
+ SL2_return_fnew_MASK = 0x1fc7,
+ SL2_return_t_BITS = 0x1f44,
+ SL2_return_t_MASK = 0x1fc7,
+ SL2_return_tnew_BITS = 0x1f46,
+ SL2_return_tnew_MASK = 0x1fc7,
+ SS1_storeb_io_BITS = 0x1000,
+ SS1_storeb_io_MASK = 0x1000,
+ SS1_storew_io_BITS = 0x0000,
+ SS1_storew_io_MASK = 0x1000,
+ SS2_allocframe_BITS = 0x1c00,
+ SS2_allocframe_MASK = 0x1e00,
+ SS2_storebi0_BITS = 0x1200,
+ SS2_storebi0_MASK = 0x1f00,
+ SS2_storebi1_BITS = 0x1300,
+ SS2_storebi1_MASK = 0x1f00,
+ SS2_stored_sp_BITS = 0x0a00,
+ SS2_stored_sp_MASK = 0x1e00,
+ SS2_storeh_io_BITS = 0x0000,
+ SS2_storeh_io_MASK = 0x1800,
+ SS2_storew_sp_BITS = 0x0800,
+ SS2_storew_sp_MASK = 0x1e00,
+ SS2_storewi0_BITS = 0x1000,
+ SS2_storewi0_MASK = 0x1f00,
+ SS2_storewi1_BITS = 0x1100,
+ SS2_storewi1_MASK = 0x1f00
};
static unsigned GetSubinstOpcode(unsigned IClass, unsigned inst, unsigned &op,
raw_ostream &os) {
switch (IClass) {
case HexagonII::HSIG_L1:
- if ((inst & V4_SL1_loadri_io_MASK) == V4_SL1_loadri_io_BITS)
- op = Hexagon::V4_SL1_loadri_io;
- else if ((inst & V4_SL1_loadrub_io_MASK) == V4_SL1_loadrub_io_BITS)
- op = Hexagon::V4_SL1_loadrub_io;
+ if ((inst & SL1_loadri_io_MASK) == SL1_loadri_io_BITS)
+ op = Hexagon::SL1_loadri_io;
+ else if ((inst & SL1_loadrub_io_MASK) == SL1_loadrub_io_BITS)
+ op = Hexagon::SL1_loadrub_io;
else {
os << "<unknown subinstruction>";
return MCDisassembler::Fail;
}
break;
case HexagonII::HSIG_L2:
- if ((inst & V4_SL2_deallocframe_MASK) == V4_SL2_deallocframe_BITS)
- op = Hexagon::V4_SL2_deallocframe;
- else if ((inst & V4_SL2_jumpr31_MASK) == V4_SL2_jumpr31_BITS)
- op = Hexagon::V4_SL2_jumpr31;
- else if ((inst & V4_SL2_jumpr31_f_MASK) == V4_SL2_jumpr31_f_BITS)
- op = Hexagon::V4_SL2_jumpr31_f;
- else if ((inst & V4_SL2_jumpr31_fnew_MASK) == V4_SL2_jumpr31_fnew_BITS)
- op = Hexagon::V4_SL2_jumpr31_fnew;
- else if ((inst & V4_SL2_jumpr31_t_MASK) == V4_SL2_jumpr31_t_BITS)
- op = Hexagon::V4_SL2_jumpr31_t;
- else if ((inst & V4_SL2_jumpr31_tnew_MASK) == V4_SL2_jumpr31_tnew_BITS)
- op = Hexagon::V4_SL2_jumpr31_tnew;
- else if ((inst & V4_SL2_loadrb_io_MASK) == V4_SL2_loadrb_io_BITS)
- op = Hexagon::V4_SL2_loadrb_io;
- else if ((inst & V4_SL2_loadrd_sp_MASK) == V4_SL2_loadrd_sp_BITS)
- op = Hexagon::V4_SL2_loadrd_sp;
- else if ((inst & V4_SL2_loadrh_io_MASK) == V4_SL2_loadrh_io_BITS)
- op = Hexagon::V4_SL2_loadrh_io;
- else if ((inst & V4_SL2_loadri_sp_MASK) == V4_SL2_loadri_sp_BITS)
- op = Hexagon::V4_SL2_loadri_sp;
- else if ((inst & V4_SL2_loadruh_io_MASK) == V4_SL2_loadruh_io_BITS)
- op = Hexagon::V4_SL2_loadruh_io;
- else if ((inst & V4_SL2_return_MASK) == V4_SL2_return_BITS)
- op = Hexagon::V4_SL2_return;
- else if ((inst & V4_SL2_return_f_MASK) == V4_SL2_return_f_BITS)
- op = Hexagon::V4_SL2_return_f;
- else if ((inst & V4_SL2_return_fnew_MASK) == V4_SL2_return_fnew_BITS)
- op = Hexagon::V4_SL2_return_fnew;
- else if ((inst & V4_SL2_return_t_MASK) == V4_SL2_return_t_BITS)
- op = Hexagon::V4_SL2_return_t;
- else if ((inst & V4_SL2_return_tnew_MASK) == V4_SL2_return_tnew_BITS)
- op = Hexagon::V4_SL2_return_tnew;
+ if ((inst & SL2_deallocframe_MASK) == SL2_deallocframe_BITS)
+ op = Hexagon::SL2_deallocframe;
+ else if ((inst & SL2_jumpr31_MASK) == SL2_jumpr31_BITS)
+ op = Hexagon::SL2_jumpr31;
+ else if ((inst & SL2_jumpr31_f_MASK) == SL2_jumpr31_f_BITS)
+ op = Hexagon::SL2_jumpr31_f;
+ else if ((inst & SL2_jumpr31_fnew_MASK) == SL2_jumpr31_fnew_BITS)
+ op = Hexagon::SL2_jumpr31_fnew;
+ else if ((inst & SL2_jumpr31_t_MASK) == SL2_jumpr31_t_BITS)
+ op = Hexagon::SL2_jumpr31_t;
+ else if ((inst & SL2_jumpr31_tnew_MASK) == SL2_jumpr31_tnew_BITS)
+ op = Hexagon::SL2_jumpr31_tnew;
+ else if ((inst & SL2_loadrb_io_MASK) == SL2_loadrb_io_BITS)
+ op = Hexagon::SL2_loadrb_io;
+ else if ((inst & SL2_loadrd_sp_MASK) == SL2_loadrd_sp_BITS)
+ op = Hexagon::SL2_loadrd_sp;
+ else if ((inst & SL2_loadrh_io_MASK) == SL2_loadrh_io_BITS)
+ op = Hexagon::SL2_loadrh_io;
+ else if ((inst & SL2_loadri_sp_MASK) == SL2_loadri_sp_BITS)
+ op = Hexagon::SL2_loadri_sp;
+ else if ((inst & SL2_loadruh_io_MASK) == SL2_loadruh_io_BITS)
+ op = Hexagon::SL2_loadruh_io;
+ else if ((inst & SL2_return_MASK) == SL2_return_BITS)
+ op = Hexagon::SL2_return;
+ else if ((inst & SL2_return_f_MASK) == SL2_return_f_BITS)
+ op = Hexagon::SL2_return_f;
+ else if ((inst & SL2_return_fnew_MASK) == SL2_return_fnew_BITS)
+ op = Hexagon::SL2_return_fnew;
+ else if ((inst & SL2_return_t_MASK) == SL2_return_t_BITS)
+ op = Hexagon::SL2_return_t;
+ else if ((inst & SL2_return_tnew_MASK) == SL2_return_tnew_BITS)
+ op = Hexagon::SL2_return_tnew;
else {
os << "<unknown subinstruction>";
return MCDisassembler::Fail;
}
break;
case HexagonII::HSIG_A:
- if ((inst & V4_SA1_addi_MASK) == V4_SA1_addi_BITS)
- op = Hexagon::V4_SA1_addi;
- else if ((inst & V4_SA1_addrx_MASK) == V4_SA1_addrx_BITS)
- op = Hexagon::V4_SA1_addrx;
- else if ((inst & V4_SA1_addsp_MASK) == V4_SA1_addsp_BITS)
- op = Hexagon::V4_SA1_addsp;
- else if ((inst & V4_SA1_and1_MASK) == V4_SA1_and1_BITS)
- op = Hexagon::V4_SA1_and1;
- else if ((inst & V4_SA1_clrf_MASK) == V4_SA1_clrf_BITS)
- op = Hexagon::V4_SA1_clrf;
- else if ((inst & V4_SA1_clrfnew_MASK) == V4_SA1_clrfnew_BITS)
- op = Hexagon::V4_SA1_clrfnew;
- else if ((inst & V4_SA1_clrt_MASK) == V4_SA1_clrt_BITS)
- op = Hexagon::V4_SA1_clrt;
- else if ((inst & V4_SA1_clrtnew_MASK) == V4_SA1_clrtnew_BITS)
- op = Hexagon::V4_SA1_clrtnew;
- else if ((inst & V4_SA1_cmpeqi_MASK) == V4_SA1_cmpeqi_BITS)
- op = Hexagon::V4_SA1_cmpeqi;
- else if ((inst & V4_SA1_combine0i_MASK) == V4_SA1_combine0i_BITS)
- op = Hexagon::V4_SA1_combine0i;
- else if ((inst & V4_SA1_combine1i_MASK) == V4_SA1_combine1i_BITS)
- op = Hexagon::V4_SA1_combine1i;
- else if ((inst & V4_SA1_combine2i_MASK) == V4_SA1_combine2i_BITS)
- op = Hexagon::V4_SA1_combine2i;
- else if ((inst & V4_SA1_combine3i_MASK) == V4_SA1_combine3i_BITS)
- op = Hexagon::V4_SA1_combine3i;
- else if ((inst & V4_SA1_combinerz_MASK) == V4_SA1_combinerz_BITS)
- op = Hexagon::V4_SA1_combinerz;
- else if ((inst & V4_SA1_combinezr_MASK) == V4_SA1_combinezr_BITS)
- op = Hexagon::V4_SA1_combinezr;
- else if ((inst & V4_SA1_dec_MASK) == V4_SA1_dec_BITS)
- op = Hexagon::V4_SA1_dec;
- else if ((inst & V4_SA1_inc_MASK) == V4_SA1_inc_BITS)
- op = Hexagon::V4_SA1_inc;
- else if ((inst & V4_SA1_seti_MASK) == V4_SA1_seti_BITS)
- op = Hexagon::V4_SA1_seti;
- else if ((inst & V4_SA1_setin1_MASK) == V4_SA1_setin1_BITS)
- op = Hexagon::V4_SA1_setin1;
- else if ((inst & V4_SA1_sxtb_MASK) == V4_SA1_sxtb_BITS)
- op = Hexagon::V4_SA1_sxtb;
- else if ((inst & V4_SA1_sxth_MASK) == V4_SA1_sxth_BITS)
- op = Hexagon::V4_SA1_sxth;
- else if ((inst & V4_SA1_tfr_MASK) == V4_SA1_tfr_BITS)
- op = Hexagon::V4_SA1_tfr;
- else if ((inst & V4_SA1_zxtb_MASK) == V4_SA1_zxtb_BITS)
- op = Hexagon::V4_SA1_zxtb;
- else if ((inst & V4_SA1_zxth_MASK) == V4_SA1_zxth_BITS)
- op = Hexagon::V4_SA1_zxth;
+ if ((inst & SA1_addi_MASK) == SA1_addi_BITS)
+ op = Hexagon::SA1_addi;
+ else if ((inst & SA1_addrx_MASK) == SA1_addrx_BITS)
+ op = Hexagon::SA1_addrx;
+ else if ((inst & SA1_addsp_MASK) == SA1_addsp_BITS)
+ op = Hexagon::SA1_addsp;
+ else if ((inst & SA1_and1_MASK) == SA1_and1_BITS)
+ op = Hexagon::SA1_and1;
+ else if ((inst & SA1_clrf_MASK) == SA1_clrf_BITS)
+ op = Hexagon::SA1_clrf;
+ else if ((inst & SA1_clrfnew_MASK) == SA1_clrfnew_BITS)
+ op = Hexagon::SA1_clrfnew;
+ else if ((inst & SA1_clrt_MASK) == SA1_clrt_BITS)
+ op = Hexagon::SA1_clrt;
+ else if ((inst & SA1_clrtnew_MASK) == SA1_clrtnew_BITS)
+ op = Hexagon::SA1_clrtnew;
+ else if ((inst & SA1_cmpeqi_MASK) == SA1_cmpeqi_BITS)
+ op = Hexagon::SA1_cmpeqi;
+ else if ((inst & SA1_combine0i_MASK) == SA1_combine0i_BITS)
+ op = Hexagon::SA1_combine0i;
+ else if ((inst & SA1_combine1i_MASK) == SA1_combine1i_BITS)
+ op = Hexagon::SA1_combine1i;
+ else if ((inst & SA1_combine2i_MASK) == SA1_combine2i_BITS)
+ op = Hexagon::SA1_combine2i;
+ else if ((inst & SA1_combine3i_MASK) == SA1_combine3i_BITS)
+ op = Hexagon::SA1_combine3i;
+ else if ((inst & SA1_combinerz_MASK) == SA1_combinerz_BITS)
+ op = Hexagon::SA1_combinerz;
+ else if ((inst & SA1_combinezr_MASK) == SA1_combinezr_BITS)
+ op = Hexagon::SA1_combinezr;
+ else if ((inst & SA1_dec_MASK) == SA1_dec_BITS)
+ op = Hexagon::SA1_dec;
+ else if ((inst & SA1_inc_MASK) == SA1_inc_BITS)
+ op = Hexagon::SA1_inc;
+ else if ((inst & SA1_seti_MASK) == SA1_seti_BITS)
+ op = Hexagon::SA1_seti;
+ else if ((inst & SA1_setin1_MASK) == SA1_setin1_BITS)
+ op = Hexagon::SA1_setin1;
+ else if ((inst & SA1_sxtb_MASK) == SA1_sxtb_BITS)
+ op = Hexagon::SA1_sxtb;
+ else if ((inst & SA1_sxth_MASK) == SA1_sxth_BITS)
+ op = Hexagon::SA1_sxth;
+ else if ((inst & SA1_tfr_MASK) == SA1_tfr_BITS)
+ op = Hexagon::SA1_tfr;
+ else if ((inst & SA1_zxtb_MASK) == SA1_zxtb_BITS)
+ op = Hexagon::SA1_zxtb;
+ else if ((inst & SA1_zxth_MASK) == SA1_zxth_BITS)
+ op = Hexagon::SA1_zxth;
else {
os << "<unknown subinstruction>";
return MCDisassembler::Fail;
}
break;
case HexagonII::HSIG_S1:
- if ((inst & V4_SS1_storeb_io_MASK) == V4_SS1_storeb_io_BITS)
- op = Hexagon::V4_SS1_storeb_io;
- else if ((inst & V4_SS1_storew_io_MASK) == V4_SS1_storew_io_BITS)
- op = Hexagon::V4_SS1_storew_io;
+ if ((inst & SS1_storeb_io_MASK) == SS1_storeb_io_BITS)
+ op = Hexagon::SS1_storeb_io;
+ else if ((inst & SS1_storew_io_MASK) == SS1_storew_io_BITS)
+ op = Hexagon::SS1_storew_io;
else {
os << "<unknown subinstruction>";
return MCDisassembler::Fail;
}
break;
case HexagonII::HSIG_S2:
- if ((inst & V4_SS2_allocframe_MASK) == V4_SS2_allocframe_BITS)
- op = Hexagon::V4_SS2_allocframe;
- else if ((inst & V4_SS2_storebi0_MASK) == V4_SS2_storebi0_BITS)
- op = Hexagon::V4_SS2_storebi0;
- else if ((inst & V4_SS2_storebi1_MASK) == V4_SS2_storebi1_BITS)
- op = Hexagon::V4_SS2_storebi1;
- else if ((inst & V4_SS2_stored_sp_MASK) == V4_SS2_stored_sp_BITS)
- op = Hexagon::V4_SS2_stored_sp;
- else if ((inst & V4_SS2_storeh_io_MASK) == V4_SS2_storeh_io_BITS)
- op = Hexagon::V4_SS2_storeh_io;
- else if ((inst & V4_SS2_storew_sp_MASK) == V4_SS2_storew_sp_BITS)
- op = Hexagon::V4_SS2_storew_sp;
- else if ((inst & V4_SS2_storewi0_MASK) == V4_SS2_storewi0_BITS)
- op = Hexagon::V4_SS2_storewi0;
- else if ((inst & V4_SS2_storewi1_MASK) == V4_SS2_storewi1_BITS)
- op = Hexagon::V4_SS2_storewi1;
+ if ((inst & SS2_allocframe_MASK) == SS2_allocframe_BITS)
+ op = Hexagon::SS2_allocframe;
+ else if ((inst & SS2_storebi0_MASK) == SS2_storebi0_BITS)
+ op = Hexagon::SS2_storebi0;
+ else if ((inst & SS2_storebi1_MASK) == SS2_storebi1_BITS)
+ op = Hexagon::SS2_storebi1;
+ else if ((inst & SS2_stored_sp_MASK) == SS2_stored_sp_BITS)
+ op = Hexagon::SS2_stored_sp;
+ else if ((inst & SS2_storeh_io_MASK) == SS2_storeh_io_BITS)
+ op = Hexagon::SS2_storeh_io;
+ else if ((inst & SS2_storew_sp_MASK) == SS2_storew_sp_BITS)
+ op = Hexagon::SS2_storew_sp;
+ else if ((inst & SS2_storewi0_MASK) == SS2_storewi0_BITS)
+ op = Hexagon::SS2_storewi0;
+ else if ((inst & SS2_storewi1_MASK) == SS2_storewi1_BITS)
+ op = Hexagon::SS2_storewi1;
else {
os << "<unknown subinstruction>";
return MCDisassembler::Fail;
@@ -1362,25 +1362,25 @@ void HexagonDisassembler::addSubinstOper
int64_t operand;
MCOperand Op;
switch (opcode) {
- case Hexagon::V4_SL2_deallocframe:
- case Hexagon::V4_SL2_jumpr31:
- case Hexagon::V4_SL2_jumpr31_f:
- case Hexagon::V4_SL2_jumpr31_fnew:
- case Hexagon::V4_SL2_jumpr31_t:
- case Hexagon::V4_SL2_jumpr31_tnew:
- case Hexagon::V4_SL2_return:
- case Hexagon::V4_SL2_return_f:
- case Hexagon::V4_SL2_return_fnew:
- case Hexagon::V4_SL2_return_t:
- case Hexagon::V4_SL2_return_tnew:
+ case Hexagon::SL2_deallocframe:
+ case Hexagon::SL2_jumpr31:
+ case Hexagon::SL2_jumpr31_f:
+ case Hexagon::SL2_jumpr31_fnew:
+ case Hexagon::SL2_jumpr31_t:
+ case Hexagon::SL2_jumpr31_tnew:
+ case Hexagon::SL2_return:
+ case Hexagon::SL2_return_f:
+ case Hexagon::SL2_return_fnew:
+ case Hexagon::SL2_return_t:
+ case Hexagon::SL2_return_tnew:
// no operands for these instructions
break;
- case Hexagon::V4_SS2_allocframe:
+ case Hexagon::SS2_allocframe:
// u 8-4{5_3}
operand = ((inst & 0x1f0) >> 4) << 3;
HexagonMCInstrInfo::addConstant(*MI, operand, getContext());
break;
- case Hexagon::V4_SL1_loadri_io:
+ case Hexagon::SL1_loadri_io:
// Rd 3-0, Rs 7-4, u 11-8{4_2}
operand = getRegFromSubinstEncoding(inst & 0xf);
Op = MCOperand::createReg(operand);
@@ -1391,7 +1391,7 @@ void HexagonDisassembler::addSubinstOper
operand = (inst & 0xf00) >> 6;
HexagonMCInstrInfo::addConstant(*MI, operand, getContext());
break;
- case Hexagon::V4_SL1_loadrub_io:
+ case Hexagon::SL1_loadrub_io:
// Rd 3-0, Rs 7-4, u 11-8
operand = getRegFromSubinstEncoding(inst & 0xf);
Op = MCOperand::createReg(operand);
@@ -1402,7 +1402,7 @@ void HexagonDisassembler::addSubinstOper
operand = (inst & 0xf00) >> 8;
HexagonMCInstrInfo::addConstant(*MI, operand, getContext());
break;
- case Hexagon::V4_SL2_loadrb_io:
+ case Hexagon::SL2_loadrb_io:
// Rd 3-0, Rs 7-4, u 10-8
operand = getRegFromSubinstEncoding(inst & 0xf);
Op = MCOperand::createReg(operand);
@@ -1413,8 +1413,8 @@ void HexagonDisassembler::addSubinstOper
operand = (inst & 0x700) >> 8;
HexagonMCInstrInfo::addConstant(*MI, operand, getContext());
break;
- case Hexagon::V4_SL2_loadrh_io:
- case Hexagon::V4_SL2_loadruh_io:
+ case Hexagon::SL2_loadrh_io:
+ case Hexagon::SL2_loadruh_io:
// Rd 3-0, Rs 7-4, u 10-8{3_1}
operand = getRegFromSubinstEncoding(inst & 0xf);
Op = MCOperand::createReg(operand);
@@ -1425,7 +1425,7 @@ void HexagonDisassembler::addSubinstOper
operand = ((inst & 0x700) >> 8) << 1;
HexagonMCInstrInfo::addConstant(*MI, operand, getContext());
break;
- case Hexagon::V4_SL2_loadrd_sp:
+ case Hexagon::SL2_loadrd_sp:
// Rdd 2-0, u 7-3{5_3}
operand = getDRegFromSubinstEncoding(inst & 0x7);
Op = MCOperand::createReg(operand);
@@ -1433,7 +1433,7 @@ void HexagonDisassembler::addSubinstOper
operand = ((inst & 0x0f8) >> 3) << 3;
HexagonMCInstrInfo::addConstant(*MI, operand, getContext());
break;
- case Hexagon::V4_SL2_loadri_sp:
+ case Hexagon::SL2_loadri_sp:
// Rd 3-0, u 8-4{5_2}
operand = getRegFromSubinstEncoding(inst & 0xf);
Op = MCOperand::createReg(operand);
@@ -1441,7 +1441,7 @@ void HexagonDisassembler::addSubinstOper
operand = ((inst & 0x1f0) >> 4) << 2;
HexagonMCInstrInfo::addConstant(*MI, operand, getContext());
break;
- case Hexagon::V4_SA1_addi:
+ case Hexagon::SA1_addi:
// Rx 3-0 (x2), s7 10-4
operand = getRegFromSubinstEncoding(inst & 0xf);
Op = MCOperand::createReg(operand);
@@ -1450,7 +1450,7 @@ void HexagonDisassembler::addSubinstOper
operand = SignExtend64<7>((inst & 0x7f0) >> 4);
HexagonMCInstrInfo::addConstant(*MI, operand, getContext());
break;
- case Hexagon::V4_SA1_addrx:
+ case Hexagon::SA1_addrx:
// Rx 3-0 (x2), Rs 7-4
operand = getRegFromSubinstEncoding(inst & 0xf);
Op = MCOperand::createReg(operand);
@@ -1460,14 +1460,14 @@ void HexagonDisassembler::addSubinstOper
Op = MCOperand::createReg(operand);
MI->addOperand(Op);
break;
- case Hexagon::V4_SA1_and1:
- case Hexagon::V4_SA1_dec:
- case Hexagon::V4_SA1_inc:
- case Hexagon::V4_SA1_sxtb:
- case Hexagon::V4_SA1_sxth:
- case Hexagon::V4_SA1_tfr:
- case Hexagon::V4_SA1_zxtb:
- case Hexagon::V4_SA1_zxth:
+ case Hexagon::SA1_and1:
+ case Hexagon::SA1_dec:
+ case Hexagon::SA1_inc:
+ case Hexagon::SA1_sxtb:
+ case Hexagon::SA1_sxth:
+ case Hexagon::SA1_tfr:
+ case Hexagon::SA1_zxtb:
+ case Hexagon::SA1_zxth:
// Rd 3-0, Rs 7-4
operand = getRegFromSubinstEncoding(inst & 0xf);
Op = MCOperand::createReg(operand);
@@ -1476,7 +1476,7 @@ void HexagonDisassembler::addSubinstOper
Op = MCOperand::createReg(operand);
MI->addOperand(Op);
break;
- case Hexagon::V4_SA1_addsp:
+ case Hexagon::SA1_addsp:
// Rd 3-0, u 9-4{6_2}
operand = getRegFromSubinstEncoding(inst & 0xf);
Op = MCOperand::createReg(operand);
@@ -1484,7 +1484,7 @@ void HexagonDisassembler::addSubinstOper
operand = ((inst & 0x3f0) >> 4) << 2;
HexagonMCInstrInfo::addConstant(*MI, operand, getContext());
break;
- case Hexagon::V4_SA1_seti:
+ case Hexagon::SA1_seti:
// Rd 3-0, u 9-4
operand = getRegFromSubinstEncoding(inst & 0xf);
Op = MCOperand::createReg(operand);
@@ -1492,20 +1492,20 @@ void HexagonDisassembler::addSubinstOper
operand = (inst & 0x3f0) >> 4;
HexagonMCInstrInfo::addConstant(*MI, operand, getContext());
break;
- case Hexagon::V4_SA1_clrf:
- case Hexagon::V4_SA1_clrfnew:
- case Hexagon::V4_SA1_clrt:
- case Hexagon::V4_SA1_clrtnew:
- case Hexagon::V4_SA1_setin1:
+ case Hexagon::SA1_clrf:
+ case Hexagon::SA1_clrfnew:
+ case Hexagon::SA1_clrt:
+ case Hexagon::SA1_clrtnew:
+ case Hexagon::SA1_setin1:
// Rd 3-0
operand = getRegFromSubinstEncoding(inst & 0xf);
Op = MCOperand::createReg(operand);
MI->addOperand(Op);
- if (opcode == Hexagon::V4_SA1_setin1)
+ if (opcode == Hexagon::SA1_setin1)
break;
MI->addOperand(MCOperand::createReg(Hexagon::P0));
break;
- case Hexagon::V4_SA1_cmpeqi:
+ case Hexagon::SA1_cmpeqi:
// Rs 7-4, u 1-0
operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
Op = MCOperand::createReg(operand);
@@ -1513,10 +1513,10 @@ void HexagonDisassembler::addSubinstOper
operand = inst & 0x3;
HexagonMCInstrInfo::addConstant(*MI, operand, getContext());
break;
- case Hexagon::V4_SA1_combine0i:
- case Hexagon::V4_SA1_combine1i:
- case Hexagon::V4_SA1_combine2i:
- case Hexagon::V4_SA1_combine3i:
+ case Hexagon::SA1_combine0i:
+ case Hexagon::SA1_combine1i:
+ case Hexagon::SA1_combine2i:
+ case Hexagon::SA1_combine3i:
// Rdd 2-0, u 6-5
operand = getDRegFromSubinstEncoding(inst & 0x7);
Op = MCOperand::createReg(operand);
@@ -1524,8 +1524,8 @@ void HexagonDisassembler::addSubinstOper
operand = (inst & 0x060) >> 5;
HexagonMCInstrInfo::addConstant(*MI, operand, getContext());
break;
- case Hexagon::V4_SA1_combinerz:
- case Hexagon::V4_SA1_combinezr:
+ case Hexagon::SA1_combinerz:
+ case Hexagon::SA1_combinezr:
// Rdd 2-0, Rs 7-4
operand = getDRegFromSubinstEncoding(inst & 0x7);
Op = MCOperand::createReg(operand);
@@ -1534,7 +1534,7 @@ void HexagonDisassembler::addSubinstOper
Op = MCOperand::createReg(operand);
MI->addOperand(Op);
break;
- case Hexagon::V4_SS1_storeb_io:
+ case Hexagon::SS1_storeb_io:
// Rs 7-4, u 11-8, Rt 3-0
operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
Op = MCOperand::createReg(operand);
@@ -1545,7 +1545,7 @@ void HexagonDisassembler::addSubinstOper
Op = MCOperand::createReg(operand);
MI->addOperand(Op);
break;
- case Hexagon::V4_SS1_storew_io:
+ case Hexagon::SS1_storew_io:
// Rs 7-4, u 11-8{4_2}, Rt 3-0
operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
Op = MCOperand::createReg(operand);
@@ -1556,8 +1556,8 @@ void HexagonDisassembler::addSubinstOper
Op = MCOperand::createReg(operand);
MI->addOperand(Op);
break;
- case Hexagon::V4_SS2_storebi0:
- case Hexagon::V4_SS2_storebi1:
+ case Hexagon::SS2_storebi0:
+ case Hexagon::SS2_storebi1:
// Rs 7-4, u 3-0
operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
Op = MCOperand::createReg(operand);
@@ -1565,8 +1565,8 @@ void HexagonDisassembler::addSubinstOper
operand = inst & 0xf;
HexagonMCInstrInfo::addConstant(*MI, operand, getContext());
break;
- case Hexagon::V4_SS2_storewi0:
- case Hexagon::V4_SS2_storewi1:
+ case Hexagon::SS2_storewi0:
+ case Hexagon::SS2_storewi1:
// Rs 7-4, u 3-0{4_2}
operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
Op = MCOperand::createReg(operand);
@@ -1574,7 +1574,7 @@ void HexagonDisassembler::addSubinstOper
operand = (inst & 0xf) << 2;
HexagonMCInstrInfo::addConstant(*MI, operand, getContext());
break;
- case Hexagon::V4_SS2_stored_sp:
+ case Hexagon::SS2_stored_sp:
// s 8-3{6_3}, Rtt 2-0
operand = SignExtend64<9>(((inst & 0x1f8) >> 3) << 3);
HexagonMCInstrInfo::addConstant(*MI, operand, getContext());
@@ -1582,7 +1582,7 @@ void HexagonDisassembler::addSubinstOper
Op = MCOperand::createReg(operand);
MI->addOperand(Op);
break;
- case Hexagon::V4_SS2_storeh_io:
+ case Hexagon::SS2_storeh_io:
// Rs 7-4, u 10-8{3_1}, Rt 3-0
operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
Op = MCOperand::createReg(operand);
@@ -1593,7 +1593,7 @@ void HexagonDisassembler::addSubinstOper
Op = MCOperand::createReg(operand);
MI->addOperand(Op);
break;
- case Hexagon::V4_SS2_storew_sp:
+ case Hexagon::SS2_storew_sp:
// u 8-4{5_2}, Rd 3-0
operand = ((inst & 0x1f0) >> 4) << 2;
HexagonMCInstrInfo::addConstant(*MI, operand, getContext());
Modified: llvm/trunk/lib/Target/Hexagon/HexagonIsetDx.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonIsetDx.td?rev=283514&r1=283513&r2=283514&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonIsetDx.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonIsetDx.td Thu Oct 6 19:15:07 2016
@@ -13,7 +13,7 @@
// SA1_combine1i: Combines.
let isCodeGenOnly = 1, hasSideEffects = 0 in
-def V4_SA1_combine1i: SUBInst <
+def SA1_combine1i: SUBInst <
(outs DoubleRegs:$Rdd),
(ins u2Imm:$u2),
"$Rdd = combine(#1, #$u2)"> {
@@ -30,7 +30,7 @@ def V4_SA1_combine1i: SUBInst <
// SL2_jumpr31_f: Indirect conditional jump if false.
// SL2_jumpr31_f -> SL2_jumpr31_fnew
let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0 in
-def V4_SL2_jumpr31_f: SUBInst <
+def SL2_jumpr31_f: SUBInst <
(outs ),
(ins ),
"if (!p0) jumpr r31"> {
@@ -40,7 +40,7 @@ def V4_SL2_jumpr31_f: SUBInst <
// SL2_deallocframe: Deallocate stack frame.
let Defs = [R31, R29, R30], Uses = [R30], isCodeGenOnly = 1, mayLoad = 1, accessSize = DoubleWordAccess in
-def V4_SL2_deallocframe: SUBInst <
+def SL2_deallocframe: SUBInst <
(outs ),
(ins ),
"deallocframe"> {
@@ -51,7 +51,7 @@ def V4_SL2_deallocframe: SUBInst <
// SL2_return_f: Deallocate stack frame and return.
// SL2_return_f -> SL2_return_fnew
let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, mayLoad = 1, accessSize = DoubleWordAccess, isBranch = 1, isIndirectBranch = 1 in
-def V4_SL2_return_f: SUBInst <
+def SL2_return_f: SUBInst <
(outs ),
(ins ),
"if (!p0) dealloc_return"> {
@@ -61,7 +61,7 @@ def V4_SL2_return_f: SUBInst <
// SA1_combine3i: Combines.
let isCodeGenOnly = 1, hasSideEffects = 0 in
-def V4_SA1_combine3i: SUBInst <
+def SA1_combine3i: SUBInst <
(outs DoubleRegs:$Rdd),
(ins u2Imm:$u2),
"$Rdd = combine(#3, #$u2)"> {
@@ -77,7 +77,7 @@ def V4_SA1_combine3i: SUBInst <
// SS2_storebi0: Store byte.
let isCodeGenOnly = 1, mayStore = 1, accessSize = ByteAccess in
-def V4_SS2_storebi0: SUBInst <
+def SS2_storebi0: SUBInst <
(outs ),
(ins IntRegs:$Rs, u4_0Imm:$u4_0),
"memb($Rs + #$u4_0)=#0"> {
@@ -91,7 +91,7 @@ def V4_SS2_storebi0: SUBInst <
// SA1_clrtnew: Clear if true.
let Uses = [P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedNew = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
-def V4_SA1_clrtnew: SUBInst <
+def SA1_clrtnew: SUBInst <
(outs IntRegs:$Rd),
(ins PredRegs:$Pu),
"if ($Pu.new) $Rd = #0"> {
@@ -104,7 +104,7 @@ def V4_SA1_clrtnew: SUBInst <
// SL2_loadruh_io: Load half.
let isCodeGenOnly = 1, mayLoad = 1, accessSize = HalfWordAccess, hasNewValue = 1, opNewValue = 0 in
-def V4_SL2_loadruh_io: SUBInst <
+def SL2_loadruh_io: SUBInst <
(outs IntRegs:$Rd),
(ins IntRegs:$Rs, u3_1Imm:$u3_1),
"$Rd = memuh($Rs + #$u3_1)"> {
@@ -120,7 +120,7 @@ def V4_SL2_loadruh_io: SUBInst <
// SL2_jumpr31_tnew: Indirect conditional jump if true.
let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isPredicatedNew = 1, isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0 in
-def V4_SL2_jumpr31_tnew: SUBInst <
+def SL2_jumpr31_tnew: SUBInst <
(outs ),
(ins ),
"if (p0.new) jumpr:nt r31"> {
@@ -130,7 +130,7 @@ def V4_SL2_jumpr31_tnew: SUBInst <
// SA1_addi: Add.
let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0, isExtendable = 1, isExtentSigned = 1, opExtentBits = 7, opExtendable = 2 in
-def V4_SA1_addi: SUBInst <
+def SA1_addi: SUBInst <
(outs IntRegs:$Rx),
(ins IntRegs:$_src_, s7Ext:$s7),
"$Rx = add($_src_, #$s7)" ,
@@ -146,7 +146,7 @@ def V4_SA1_addi: SUBInst <
// SL1_loadrub_io: Load byte.
let isCodeGenOnly = 1, mayLoad = 1, accessSize = ByteAccess, hasNewValue = 1, opNewValue = 0 in
-def V4_SL1_loadrub_io: SUBInst <
+def SL1_loadrub_io: SUBInst <
(outs IntRegs:$Rd),
(ins IntRegs:$Rs, u4_0Imm:$u4_0),
"$Rd = memub($Rs + #$u4_0)"> {
@@ -162,7 +162,7 @@ def V4_SL1_loadrub_io: SUBInst <
// SL1_loadri_io: Load word.
let isCodeGenOnly = 1, mayLoad = 1, accessSize = WordAccess, hasNewValue = 1, opNewValue = 0 in
-def V4_SL1_loadri_io: SUBInst <
+def SL1_loadri_io: SUBInst <
(outs IntRegs:$Rd),
(ins IntRegs:$Rs, u4_2Imm:$u4_2),
"$Rd = memw($Rs + #$u4_2)"> {
@@ -178,7 +178,7 @@ def V4_SL1_loadri_io: SUBInst <
// SA1_cmpeqi: Compareimmed.
let Defs = [P0], isCodeGenOnly = 1, hasSideEffects = 0 in
-def V4_SA1_cmpeqi: SUBInst <
+def SA1_cmpeqi: SUBInst <
(outs ),
(ins IntRegs:$Rs, u2Imm:$u2),
"p0 = cmp.eq($Rs, #$u2)"> {
@@ -192,7 +192,7 @@ def V4_SA1_cmpeqi: SUBInst <
// SA1_combinerz: Combines.
let isCodeGenOnly = 1, hasSideEffects = 0 in
-def V4_SA1_combinerz: SUBInst <
+def SA1_combinerz: SUBInst <
(outs DoubleRegs:$Rdd),
(ins IntRegs:$Rs),
"$Rdd = combine($Rs, #0)"> {
@@ -209,7 +209,7 @@ def V4_SA1_combinerz: SUBInst <
// SL2_return_t: Deallocate stack frame and return.
// SL2_return_t -> SL2_return_tnew
let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, mayLoad = 1, accessSize = DoubleWordAccess, isBranch = 1, isIndirectBranch = 1 in
-def V4_SL2_return_t: SUBInst <
+def SL2_return_t: SUBInst <
(outs ),
(ins ),
"if (p0) dealloc_return"> {
@@ -219,7 +219,7 @@ def V4_SL2_return_t: SUBInst <
// SS2_allocframe: Allocate stack frame.
let Defs = [R29, R30], Uses = [R30, R31, R29], isCodeGenOnly = 1, mayStore = 1, accessSize = DoubleWordAccess in
-def V4_SS2_allocframe: SUBInst <
+def SS2_allocframe: SUBInst <
(outs ),
(ins u5_3Imm:$u5_3),
"allocframe(#$u5_3)"> {
@@ -231,7 +231,7 @@ def V4_SS2_allocframe: SUBInst <
// SS2_storeh_io: Store half.
let isCodeGenOnly = 1, mayStore = 1, accessSize = HalfWordAccess in
-def V4_SS2_storeh_io: SUBInst <
+def SS2_storeh_io: SUBInst <
(outs ),
(ins IntRegs:$Rs, u3_1Imm:$u3_1, IntRegs:$Rt),
"memh($Rs + #$u3_1) = $Rt"> {
@@ -247,7 +247,7 @@ def V4_SS2_storeh_io: SUBInst <
// SS2_storewi0: Store word.
let isCodeGenOnly = 1, mayStore = 1, accessSize = WordAccess in
-def V4_SS2_storewi0: SUBInst <
+def SS2_storewi0: SUBInst <
(outs ),
(ins IntRegs:$Rs, u4_2Imm:$u4_2),
"memw($Rs + #$u4_2)=#0"> {
@@ -261,7 +261,7 @@ def V4_SS2_storewi0: SUBInst <
// SS2_storewi1: Store word.
let isCodeGenOnly = 1, mayStore = 1, accessSize = WordAccess in
-def V4_SS2_storewi1: SUBInst <
+def SS2_storewi1: SUBInst <
(outs ),
(ins IntRegs:$Rs, u4_2Imm:$u4_2),
"memw($Rs + #$u4_2)=#1"> {
@@ -275,7 +275,7 @@ def V4_SS2_storewi1: SUBInst <
// SL2_jumpr31: Indirect conditional jump if true.
let Defs = [PC], Uses = [R31], isCodeGenOnly = 1, isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0 in
-def V4_SL2_jumpr31: SUBInst <
+def SL2_jumpr31: SUBInst <
(outs ),
(ins ),
"jumpr r31"> {
@@ -285,7 +285,7 @@ def V4_SL2_jumpr31: SUBInst <
// SA1_combinezr: Combines.
let isCodeGenOnly = 1, hasSideEffects = 0 in
-def V4_SA1_combinezr: SUBInst <
+def SA1_combinezr: SUBInst <
(outs DoubleRegs:$Rdd),
(ins IntRegs:$Rs),
"$Rdd = combine(#0, $Rs)"> {
@@ -301,7 +301,7 @@ def V4_SA1_combinezr: SUBInst <
// SL2_loadrh_io: Load half.
let isCodeGenOnly = 1, mayLoad = 1, accessSize = HalfWordAccess, hasNewValue = 1, opNewValue = 0 in
-def V4_SL2_loadrh_io: SUBInst <
+def SL2_loadrh_io: SUBInst <
(outs IntRegs:$Rd),
(ins IntRegs:$Rs, u3_1Imm:$u3_1),
"$Rd = memh($Rs + #$u3_1)"> {
@@ -317,7 +317,7 @@ def V4_SL2_loadrh_io: SUBInst <
// SA1_addrx: Add.
let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
-def V4_SA1_addrx: SUBInst <
+def SA1_addrx: SUBInst <
(outs IntRegs:$Rx),
(ins IntRegs:$_src_, IntRegs:$Rs),
"$Rx = add($_src_, $Rs)" ,
@@ -333,7 +333,7 @@ def V4_SA1_addrx: SUBInst <
// SA1_setin1: Set to -1.
let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
-def V4_SA1_setin1: SUBInst <
+def SA1_setin1: SUBInst <
(outs IntRegs:$Rd),
(ins ),
"$Rd = #{-1}"> {
@@ -346,7 +346,7 @@ def V4_SA1_setin1: SUBInst <
// SA1_sxth: Sxth.
let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
-def V4_SA1_sxth: SUBInst <
+def SA1_sxth: SUBInst <
(outs IntRegs:$Rd),
(ins IntRegs:$Rs),
"$Rd = sxth($Rs)"> {
@@ -360,7 +360,7 @@ def V4_SA1_sxth: SUBInst <
// SA1_combine0i: Combines.
let isCodeGenOnly = 1, hasSideEffects = 0 in
-def V4_SA1_combine0i: SUBInst <
+def SA1_combine0i: SUBInst <
(outs DoubleRegs:$Rdd),
(ins u2Imm:$u2),
"$Rdd = combine(#0, #$u2)"> {
@@ -376,7 +376,7 @@ def V4_SA1_combine0i: SUBInst <
// SA1_combine2i: Combines.
let isCodeGenOnly = 1, hasSideEffects = 0 in
-def V4_SA1_combine2i: SUBInst <
+def SA1_combine2i: SUBInst <
(outs DoubleRegs:$Rdd),
(ins u2Imm:$u2),
"$Rdd = combine(#2, #$u2)"> {
@@ -392,7 +392,7 @@ def V4_SA1_combine2i: SUBInst <
// SA1_sxtb: Sxtb.
let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
-def V4_SA1_sxtb: SUBInst <
+def SA1_sxtb: SUBInst <
(outs IntRegs:$Rd),
(ins IntRegs:$Rs),
"$Rd = sxtb($Rs)"> {
@@ -407,7 +407,7 @@ def V4_SA1_sxtb: SUBInst <
// SA1_clrf: Clear if false.
// SA1_clrf -> SA1_clrfnew
let Uses = [P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
-def V4_SA1_clrf: SUBInst <
+def SA1_clrf: SUBInst <
(outs IntRegs:$Rd),
(ins PredRegs:$Pu),
"if (!$Pu) $Rd = #0"> {
@@ -420,7 +420,7 @@ def V4_SA1_clrf: SUBInst <
// SL2_loadrb_io: Load byte.
let isCodeGenOnly = 1, mayLoad = 1, accessSize = ByteAccess, hasNewValue = 1, opNewValue = 0 in
-def V4_SL2_loadrb_io: SUBInst <
+def SL2_loadrb_io: SUBInst <
(outs IntRegs:$Rd),
(ins IntRegs:$Rs, u3_0Imm:$u3_0),
"$Rd = memb($Rs + #$u3_0)"> {
@@ -436,7 +436,7 @@ def V4_SL2_loadrb_io: SUBInst <
// SA1_tfr: Tfr.
let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
-def V4_SA1_tfr: SUBInst <
+def SA1_tfr: SUBInst <
(outs IntRegs:$Rd),
(ins IntRegs:$Rs),
"$Rd = $Rs"> {
@@ -450,7 +450,7 @@ def V4_SA1_tfr: SUBInst <
// SL2_loadrd_sp: Load dword.
let Uses = [R29], isCodeGenOnly = 1, mayLoad = 1, accessSize = DoubleWordAccess in
-def V4_SL2_loadrd_sp: SUBInst <
+def SL2_loadrd_sp: SUBInst <
(outs DoubleRegs:$Rdd),
(ins u5_3Imm:$u5_3),
"$Rdd = memd(r29 + #$u5_3)"> {
@@ -464,7 +464,7 @@ def V4_SL2_loadrd_sp: SUBInst <
// SA1_and1: And #1.
let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
-def V4_SA1_and1: SUBInst <
+def SA1_and1: SUBInst <
(outs IntRegs:$Rd),
(ins IntRegs:$Rs),
"$Rd = and($Rs, #1)"> {
@@ -478,7 +478,7 @@ def V4_SA1_and1: SUBInst <
// SS2_storebi1: Store byte.
let isCodeGenOnly = 1, mayStore = 1, accessSize = ByteAccess in
-def V4_SS2_storebi1: SUBInst <
+def SS2_storebi1: SUBInst <
(outs ),
(ins IntRegs:$Rs, u4_0Imm:$u4_0),
"memb($Rs + #$u4_0)=#1"> {
@@ -492,7 +492,7 @@ def V4_SS2_storebi1: SUBInst <
// SA1_inc: Inc.
let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
-def V4_SA1_inc: SUBInst <
+def SA1_inc: SUBInst <
(outs IntRegs:$Rd),
(ins IntRegs:$Rs),
"$Rd = add($Rs, #1)"> {
@@ -506,7 +506,7 @@ def V4_SA1_inc: SUBInst <
// SS2_stored_sp: Store dword.
let Uses = [R29], isCodeGenOnly = 1, mayStore = 1, accessSize = DoubleWordAccess in
-def V4_SS2_stored_sp: SUBInst <
+def SS2_stored_sp: SUBInst <
(outs ),
(ins s6_3Imm:$s6_3, DoubleRegs:$Rtt),
"memd(r29 + #$s6_3) = $Rtt"> {
@@ -520,7 +520,7 @@ def V4_SS2_stored_sp: SUBInst <
// SS2_storew_sp: Store word.
let Uses = [R29], isCodeGenOnly = 1, mayStore = 1, accessSize = WordAccess in
-def V4_SS2_storew_sp: SUBInst <
+def SS2_storew_sp: SUBInst <
(outs ),
(ins u5_2Imm:$u5_2, IntRegs:$Rt),
"memw(r29 + #$u5_2) = $Rt"> {
@@ -534,7 +534,7 @@ def V4_SS2_storew_sp: SUBInst <
// SL2_jumpr31_fnew: Indirect conditional jump if false.
let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, isPredicatedNew = 1, isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0 in
-def V4_SL2_jumpr31_fnew: SUBInst <
+def SL2_jumpr31_fnew: SUBInst <
(outs ),
(ins ),
"if (!p0.new) jumpr:nt r31"> {
@@ -545,7 +545,7 @@ def V4_SL2_jumpr31_fnew: SUBInst <
// SA1_clrt: Clear if true.
// SA1_clrt -> SA1_clrtnew
let Uses = [P0], isCodeGenOnly = 1, isPredicated = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
-def V4_SA1_clrt: SUBInst <
+def SA1_clrt: SUBInst <
(outs IntRegs:$Rd),
(ins PredRegs:$Pu),
"if ($Pu) $Rd = #0"> {
@@ -558,7 +558,7 @@ def V4_SA1_clrt: SUBInst <
// SL2_return: Deallocate stack frame and return.
let Defs = [PC, R31, R29, R30], Uses = [R30], isCodeGenOnly = 1, mayLoad = 1, accessSize = DoubleWordAccess, isBranch = 1, isIndirectBranch = 1 in
-def V4_SL2_return: SUBInst <
+def SL2_return: SUBInst <
(outs ),
(ins ),
"dealloc_return"> {
@@ -568,7 +568,7 @@ def V4_SL2_return: SUBInst <
// SA1_dec: Dec.
let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
-def V4_SA1_dec: SUBInst <
+def SA1_dec: SUBInst <
(outs IntRegs:$Rd),
(ins IntRegs:$Rs),
"$Rd = add($Rs,#{-1})"> {
@@ -582,7 +582,7 @@ def V4_SA1_dec: SUBInst <
// SA1_seti: Set immed.
let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0, isExtendable = 1, isExtentSigned = 0, opExtentBits = 6, opExtendable = 1 in
-def V4_SA1_seti: SUBInst <
+def SA1_seti: SUBInst <
(outs IntRegs:$Rd),
(ins u6Ext:$u6),
"$Rd = #$u6"> {
@@ -597,7 +597,7 @@ def V4_SA1_seti: SUBInst <
// SL2_jumpr31_t: Indirect conditional jump if true.
// SL2_jumpr31_t -> SL2_jumpr31_tnew
let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0 in
-def V4_SL2_jumpr31_t: SUBInst <
+def SL2_jumpr31_t: SUBInst <
(outs ),
(ins ),
"if (p0) jumpr r31"> {
@@ -607,7 +607,7 @@ def V4_SL2_jumpr31_t: SUBInst <
// SA1_clrfnew: Clear if false.
let Uses = [P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, isPredicatedNew = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
-def V4_SA1_clrfnew: SUBInst <
+def SA1_clrfnew: SUBInst <
(outs IntRegs:$Rd),
(ins PredRegs:$Pu),
"if (!$Pu.new) $Rd = #0"> {
@@ -620,7 +620,7 @@ def V4_SA1_clrfnew: SUBInst <
// SS1_storew_io: Store word.
let isCodeGenOnly = 1, mayStore = 1, accessSize = WordAccess in
-def V4_SS1_storew_io: SUBInst <
+def SS1_storew_io: SUBInst <
(outs ),
(ins IntRegs:$Rs, u4_2Imm:$u4_2, IntRegs:$Rt),
"memw($Rs + #$u4_2) = $Rt"> {
@@ -636,7 +636,7 @@ def V4_SS1_storew_io: SUBInst <
// SA1_zxtb: Zxtb.
let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
-def V4_SA1_zxtb: SUBInst <
+def SA1_zxtb: SUBInst <
(outs IntRegs:$Rd),
(ins IntRegs:$Rs),
"$Rd = and($Rs, #255)"> {
@@ -650,7 +650,7 @@ def V4_SA1_zxtb: SUBInst <
// SA1_addsp: Add.
let Uses = [R29], isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
-def V4_SA1_addsp: SUBInst <
+def SA1_addsp: SUBInst <
(outs IntRegs:$Rd),
(ins u6_2Imm:$u6_2),
"$Rd = add(r29, #$u6_2)"> {
@@ -664,7 +664,7 @@ def V4_SA1_addsp: SUBInst <
// SL2_loadri_sp: Load word.
let Uses = [R29], isCodeGenOnly = 1, mayLoad = 1, accessSize = WordAccess, hasNewValue = 1, opNewValue = 0 in
-def V4_SL2_loadri_sp: SUBInst <
+def SL2_loadri_sp: SUBInst <
(outs IntRegs:$Rd),
(ins u5_2Imm:$u5_2),
"$Rd = memw(r29 + #$u5_2)"> {
@@ -678,7 +678,7 @@ def V4_SL2_loadri_sp: SUBInst <
// SS1_storeb_io: Store byte.
let isCodeGenOnly = 1, mayStore = 1, accessSize = ByteAccess in
-def V4_SS1_storeb_io: SUBInst <
+def SS1_storeb_io: SUBInst <
(outs ),
(ins IntRegs:$Rs, u4_0Imm:$u4_0, IntRegs:$Rt),
"memb($Rs + #$u4_0) = $Rt"> {
@@ -694,7 +694,7 @@ def V4_SS1_storeb_io: SUBInst <
// SL2_return_tnew: Deallocate stack frame and return.
let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedNew = 1, mayLoad = 1, accessSize = DoubleWordAccess, isBranch = 1, isIndirectBranch = 1 in
-def V4_SL2_return_tnew: SUBInst <
+def SL2_return_tnew: SUBInst <
(outs ),
(ins ),
"if (p0.new) dealloc_return:nt"> {
@@ -704,7 +704,7 @@ def V4_SL2_return_tnew: SUBInst <
// SL2_return_fnew: Deallocate stack frame and return.
let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, isPredicatedNew = 1, mayLoad = 1, accessSize = DoubleWordAccess, isBranch = 1, isIndirectBranch = 1 in
-def V4_SL2_return_fnew: SUBInst <
+def SL2_return_fnew: SUBInst <
(outs ),
(ins ),
"if (!p0.new) dealloc_return:nt"> {
@@ -714,7 +714,7 @@ def V4_SL2_return_fnew: SUBInst <
// SA1_zxth: Zxth.
let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
-def V4_SA1_zxth: SUBInst <
+def SA1_zxth: SUBInst <
(outs IntRegs:$Rd),
(ins IntRegs:$Rs),
"$Rd = zxth($Rs)"> {
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp?rev=283514&r1=283513&r2=283514&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp Thu Oct 6 19:15:07 2016
@@ -27,58 +27,58 @@ using namespace Hexagon;
// pair table of subInstructions with opcodes
static const std::pair<unsigned, unsigned> opcodeData[] = {
- std::make_pair((unsigned)V4_SA1_addi, 0),
- std::make_pair((unsigned)V4_SA1_addrx, 6144),
- std::make_pair((unsigned)V4_SA1_addsp, 3072),
- std::make_pair((unsigned)V4_SA1_and1, 4608),
- std::make_pair((unsigned)V4_SA1_clrf, 6768),
- std::make_pair((unsigned)V4_SA1_clrfnew, 6736),
- std::make_pair((unsigned)V4_SA1_clrt, 6752),
- std::make_pair((unsigned)V4_SA1_clrtnew, 6720),
- std::make_pair((unsigned)V4_SA1_cmpeqi, 6400),
- std::make_pair((unsigned)V4_SA1_combine0i, 7168),
- std::make_pair((unsigned)V4_SA1_combine1i, 7176),
- std::make_pair((unsigned)V4_SA1_combine2i, 7184),
- std::make_pair((unsigned)V4_SA1_combine3i, 7192),
- std::make_pair((unsigned)V4_SA1_combinerz, 7432),
- std::make_pair((unsigned)V4_SA1_combinezr, 7424),
- std::make_pair((unsigned)V4_SA1_dec, 4864),
- std::make_pair((unsigned)V4_SA1_inc, 4352),
- std::make_pair((unsigned)V4_SA1_seti, 2048),
- std::make_pair((unsigned)V4_SA1_setin1, 6656),
- std::make_pair((unsigned)V4_SA1_sxtb, 5376),
- std::make_pair((unsigned)V4_SA1_sxth, 5120),
- std::make_pair((unsigned)V4_SA1_tfr, 4096),
- std::make_pair((unsigned)V4_SA1_zxtb, 5888),
- std::make_pair((unsigned)V4_SA1_zxth, 5632),
- std::make_pair((unsigned)V4_SL1_loadri_io, 0),
- std::make_pair((unsigned)V4_SL1_loadrub_io, 4096),
- std::make_pair((unsigned)V4_SL2_deallocframe, 7936),
- std::make_pair((unsigned)V4_SL2_jumpr31, 8128),
- std::make_pair((unsigned)V4_SL2_jumpr31_f, 8133),
- std::make_pair((unsigned)V4_SL2_jumpr31_fnew, 8135),
- std::make_pair((unsigned)V4_SL2_jumpr31_t, 8132),
- std::make_pair((unsigned)V4_SL2_jumpr31_tnew, 8134),
- std::make_pair((unsigned)V4_SL2_loadrb_io, 4096),
- std::make_pair((unsigned)V4_SL2_loadrd_sp, 7680),
- std::make_pair((unsigned)V4_SL2_loadrh_io, 0),
- std::make_pair((unsigned)V4_SL2_loadri_sp, 7168),
- std::make_pair((unsigned)V4_SL2_loadruh_io, 2048),
- std::make_pair((unsigned)V4_SL2_return, 8000),
- std::make_pair((unsigned)V4_SL2_return_f, 8005),
- std::make_pair((unsigned)V4_SL2_return_fnew, 8007),
- std::make_pair((unsigned)V4_SL2_return_t, 8004),
- std::make_pair((unsigned)V4_SL2_return_tnew, 8006),
- std::make_pair((unsigned)V4_SS1_storeb_io, 4096),
- std::make_pair((unsigned)V4_SS1_storew_io, 0),
- std::make_pair((unsigned)V4_SS2_allocframe, 7168),
- std::make_pair((unsigned)V4_SS2_storebi0, 4608),
- std::make_pair((unsigned)V4_SS2_storebi1, 4864),
- std::make_pair((unsigned)V4_SS2_stored_sp, 2560),
- std::make_pair((unsigned)V4_SS2_storeh_io, 0),
- std::make_pair((unsigned)V4_SS2_storew_sp, 2048),
- std::make_pair((unsigned)V4_SS2_storewi0, 4096),
- std::make_pair((unsigned)V4_SS2_storewi1, 4352)};
+ std::make_pair((unsigned)SA1_addi, 0),
+ std::make_pair((unsigned)SA1_addrx, 6144),
+ std::make_pair((unsigned)SA1_addsp, 3072),
+ std::make_pair((unsigned)SA1_and1, 4608),
+ std::make_pair((unsigned)SA1_clrf, 6768),
+ std::make_pair((unsigned)SA1_clrfnew, 6736),
+ std::make_pair((unsigned)SA1_clrt, 6752),
+ std::make_pair((unsigned)SA1_clrtnew, 6720),
+ std::make_pair((unsigned)SA1_cmpeqi, 6400),
+ std::make_pair((unsigned)SA1_combine0i, 7168),
+ std::make_pair((unsigned)SA1_combine1i, 7176),
+ std::make_pair((unsigned)SA1_combine2i, 7184),
+ std::make_pair((unsigned)SA1_combine3i, 7192),
+ std::make_pair((unsigned)SA1_combinerz, 7432),
+ std::make_pair((unsigned)SA1_combinezr, 7424),
+ std::make_pair((unsigned)SA1_dec, 4864),
+ std::make_pair((unsigned)SA1_inc, 4352),
+ std::make_pair((unsigned)SA1_seti, 2048),
+ std::make_pair((unsigned)SA1_setin1, 6656),
+ std::make_pair((unsigned)SA1_sxtb, 5376),
+ std::make_pair((unsigned)SA1_sxth, 5120),
+ std::make_pair((unsigned)SA1_tfr, 4096),
+ std::make_pair((unsigned)SA1_zxtb, 5888),
+ std::make_pair((unsigned)SA1_zxth, 5632),
+ std::make_pair((unsigned)SL1_loadri_io, 0),
+ std::make_pair((unsigned)SL1_loadrub_io, 4096),
+ std::make_pair((unsigned)SL2_deallocframe, 7936),
+ std::make_pair((unsigned)SL2_jumpr31, 8128),
+ std::make_pair((unsigned)SL2_jumpr31_f, 8133),
+ std::make_pair((unsigned)SL2_jumpr31_fnew, 8135),
+ std::make_pair((unsigned)SL2_jumpr31_t, 8132),
+ std::make_pair((unsigned)SL2_jumpr31_tnew, 8134),
+ std::make_pair((unsigned)SL2_loadrb_io, 4096),
+ std::make_pair((unsigned)SL2_loadrd_sp, 7680),
+ std::make_pair((unsigned)SL2_loadrh_io, 0),
+ std::make_pair((unsigned)SL2_loadri_sp, 7168),
+ std::make_pair((unsigned)SL2_loadruh_io, 2048),
+ std::make_pair((unsigned)SL2_return, 8000),
+ std::make_pair((unsigned)SL2_return_f, 8005),
+ std::make_pair((unsigned)SL2_return_fnew, 8007),
+ std::make_pair((unsigned)SL2_return_t, 8004),
+ std::make_pair((unsigned)SL2_return_tnew, 8006),
+ std::make_pair((unsigned)SS1_storeb_io, 4096),
+ std::make_pair((unsigned)SS1_storew_io, 0),
+ std::make_pair((unsigned)SS2_allocframe, 7168),
+ std::make_pair((unsigned)SS2_storebi0, 4608),
+ std::make_pair((unsigned)SS2_storebi1, 4864),
+ std::make_pair((unsigned)SS2_stored_sp, 2560),
+ std::make_pair((unsigned)SS2_storeh_io, 0),
+ std::make_pair((unsigned)SS2_storew_sp, 2048),
+ std::make_pair((unsigned)SS2_storewi0, 4096),
+ std::make_pair((unsigned)SS2_storewi1, 4352)};
bool HexagonMCInstrInfo::isDuplexPairMatch(unsigned Ga, unsigned Gb) {
switch (Ga) {
@@ -694,54 +694,54 @@ MCInst HexagonMCInstrInfo::deriveSubInst
Absolute = Inst.getOperand(2).getExpr()->evaluateAsAbsolute(Value);
assert(Absolute);(void)Absolute;
if (Value == 1) {
- Result.setOpcode(Hexagon::V4_SA1_inc);
+ Result.setOpcode(Hexagon::SA1_inc);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break;
} // 1,2 SUBInst $Rd = add($Rs, #1)
else if (Value == -1) {
- Result.setOpcode(Hexagon::V4_SA1_dec);
+ Result.setOpcode(Hexagon::SA1_dec);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break;
} // 1,2 SUBInst $Rd = add($Rs,#-1)
else if (Inst.getOperand(1).getReg() == Hexagon::R29) {
- Result.setOpcode(Hexagon::V4_SA1_addsp);
+ Result.setOpcode(Hexagon::SA1_addsp);
addOps(Result, Inst, 0);
addOps(Result, Inst, 2);
break;
} // 1,3 SUBInst $Rd = add(r29, #$u6_2)
else {
- Result.setOpcode(Hexagon::V4_SA1_addi);
+ Result.setOpcode(Hexagon::SA1_addi);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
addOps(Result, Inst, 2);
break;
} // 1,2,3 SUBInst $Rx = add($Rx, #$s7)
case Hexagon::A2_add:
- Result.setOpcode(Hexagon::V4_SA1_addrx);
+ Result.setOpcode(Hexagon::SA1_addrx);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
addOps(Result, Inst, 2);
break; // 1,2,3 SUBInst $Rx = add($_src_, $Rs)
case Hexagon::S2_allocframe:
- Result.setOpcode(Hexagon::V4_SS2_allocframe);
+ Result.setOpcode(Hexagon::SS2_allocframe);
addOps(Result, Inst, 0);
break; // 1 SUBInst allocframe(#$u5_3)
case Hexagon::A2_andir:
if (minConstant(Inst, 2) == 255) {
- Result.setOpcode(Hexagon::V4_SA1_zxtb);
+ Result.setOpcode(Hexagon::SA1_zxtb);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 1,2 $Rd = and($Rs, #255)
} else {
- Result.setOpcode(Hexagon::V4_SA1_and1);
+ Result.setOpcode(Hexagon::SA1_and1);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 1,2 SUBInst $Rd = and($Rs, #1)
}
case Hexagon::C2_cmpeqi:
- Result.setOpcode(Hexagon::V4_SA1_cmpeqi);
+ Result.setOpcode(Hexagon::SA1_cmpeqi);
addOps(Result, Inst, 1);
addOps(Result, Inst, 2);
break; // 2,3 SUBInst p0 = cmp.eq($Rs, #$u2)
@@ -750,115 +750,115 @@ MCInst HexagonMCInstrInfo::deriveSubInst
Absolute = Inst.getOperand(1).getExpr()->evaluateAsAbsolute(Value);
assert(Absolute);(void)Absolute;
if (Value == 1) {
- Result.setOpcode(Hexagon::V4_SA1_combine1i);
+ Result.setOpcode(Hexagon::SA1_combine1i);
addOps(Result, Inst, 0);
addOps(Result, Inst, 2);
break; // 1,3 SUBInst $Rdd = combine(#1, #$u2)
}
if (Value == 3) {
- Result.setOpcode(Hexagon::V4_SA1_combine3i);
+ Result.setOpcode(Hexagon::SA1_combine3i);
addOps(Result, Inst, 0);
addOps(Result, Inst, 2);
break; // 1,3 SUBInst $Rdd = combine(#3, #$u2)
}
if (Value == 0) {
- Result.setOpcode(Hexagon::V4_SA1_combine0i);
+ Result.setOpcode(Hexagon::SA1_combine0i);
addOps(Result, Inst, 0);
addOps(Result, Inst, 2);
break; // 1,3 SUBInst $Rdd = combine(#0, #$u2)
}
if (Value == 2) {
- Result.setOpcode(Hexagon::V4_SA1_combine2i);
+ Result.setOpcode(Hexagon::SA1_combine2i);
addOps(Result, Inst, 0);
addOps(Result, Inst, 2);
break; // 1,3 SUBInst $Rdd = combine(#2, #$u2)
}
case Hexagon::A4_combineir:
- Result.setOpcode(Hexagon::V4_SA1_combinezr);
+ Result.setOpcode(Hexagon::SA1_combinezr);
addOps(Result, Inst, 0);
addOps(Result, Inst, 2);
break; // 1,3 SUBInst $Rdd = combine(#0, $Rs)
case Hexagon::A4_combineri:
- Result.setOpcode(Hexagon::V4_SA1_combinerz);
+ Result.setOpcode(Hexagon::SA1_combinerz);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 1,2 SUBInst $Rdd = combine($Rs, #0)
case Hexagon::L4_return_tnew_pnt:
case Hexagon::L4_return_tnew_pt:
- Result.setOpcode(Hexagon::V4_SL2_return_tnew);
+ Result.setOpcode(Hexagon::SL2_return_tnew);
break; // none SUBInst if (p0.new) dealloc_return:nt
case Hexagon::L4_return_fnew_pnt:
case Hexagon::L4_return_fnew_pt:
- Result.setOpcode(Hexagon::V4_SL2_return_fnew);
+ Result.setOpcode(Hexagon::SL2_return_fnew);
break; // none SUBInst if (!p0.new) dealloc_return:nt
case Hexagon::L4_return_f:
- Result.setOpcode(Hexagon::V4_SL2_return_f);
+ Result.setOpcode(Hexagon::SL2_return_f);
break; // none SUBInst if (!p0) dealloc_return
case Hexagon::L4_return_t:
- Result.setOpcode(Hexagon::V4_SL2_return_t);
+ Result.setOpcode(Hexagon::SL2_return_t);
break; // none SUBInst if (p0) dealloc_return
case Hexagon::L4_return:
- Result.setOpcode(Hexagon::V4_SL2_return);
+ Result.setOpcode(Hexagon::SL2_return);
break; // none SUBInst dealloc_return
case Hexagon::L2_deallocframe:
- Result.setOpcode(Hexagon::V4_SL2_deallocframe);
+ Result.setOpcode(Hexagon::SL2_deallocframe);
break; // none SUBInst deallocframe
case Hexagon::EH_RETURN_JMPR:
case Hexagon::J2_jumpr:
- Result.setOpcode(Hexagon::V4_SL2_jumpr31);
+ Result.setOpcode(Hexagon::SL2_jumpr31);
break; // none SUBInst jumpr r31
case Hexagon::J2_jumprf:
- Result.setOpcode(Hexagon::V4_SL2_jumpr31_f);
+ Result.setOpcode(Hexagon::SL2_jumpr31_f);
break; // none SUBInst if (!p0) jumpr r31
case Hexagon::J2_jumprfnew:
case Hexagon::J2_jumprfnewpt:
- Result.setOpcode(Hexagon::V4_SL2_jumpr31_fnew);
+ Result.setOpcode(Hexagon::SL2_jumpr31_fnew);
break; // none SUBInst if (!p0.new) jumpr:nt r31
case Hexagon::J2_jumprt:
- Result.setOpcode(Hexagon::V4_SL2_jumpr31_t);
+ Result.setOpcode(Hexagon::SL2_jumpr31_t);
break; // none SUBInst if (p0) jumpr r31
case Hexagon::J2_jumprtnew:
case Hexagon::J2_jumprtnewpt:
- Result.setOpcode(Hexagon::V4_SL2_jumpr31_tnew);
+ Result.setOpcode(Hexagon::SL2_jumpr31_tnew);
break; // none SUBInst if (p0.new) jumpr:nt r31
case Hexagon::L2_loadrb_io:
- Result.setOpcode(Hexagon::V4_SL2_loadrb_io);
+ Result.setOpcode(Hexagon::SL2_loadrb_io);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
addOps(Result, Inst, 2);
break; // 1,2,3 SUBInst $Rd = memb($Rs + #$u3_0)
case Hexagon::L2_loadrd_io:
- Result.setOpcode(Hexagon::V4_SL2_loadrd_sp);
+ Result.setOpcode(Hexagon::SL2_loadrd_sp);
addOps(Result, Inst, 0);
addOps(Result, Inst, 2);
break; // 1,3 SUBInst $Rdd = memd(r29 + #$u5_3)
case Hexagon::L2_loadrh_io:
- Result.setOpcode(Hexagon::V4_SL2_loadrh_io);
+ Result.setOpcode(Hexagon::SL2_loadrh_io);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
addOps(Result, Inst, 2);
break; // 1,2,3 SUBInst $Rd = memh($Rs + #$u3_1)
case Hexagon::L2_loadrub_io:
- Result.setOpcode(Hexagon::V4_SL1_loadrub_io);
+ Result.setOpcode(Hexagon::SL1_loadrub_io);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
addOps(Result, Inst, 2);
break; // 1,2,3 SUBInst $Rd = memub($Rs + #$u4_0)
case Hexagon::L2_loadruh_io:
- Result.setOpcode(Hexagon::V4_SL2_loadruh_io);
+ Result.setOpcode(Hexagon::SL2_loadruh_io);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
addOps(Result, Inst, 2);
break; // 1,2,3 SUBInst $Rd = memuh($Rs + #$u3_1)
case Hexagon::L2_loadri_io:
if (Inst.getOperand(1).getReg() == Hexagon::R29) {
- Result.setOpcode(Hexagon::V4_SL2_loadri_sp);
+ Result.setOpcode(Hexagon::SL2_loadri_sp);
addOps(Result, Inst, 0);
addOps(Result, Inst, 2);
break; // 2 1,3 SUBInst $Rd = memw(r29 + #$u5_2)
} else {
- Result.setOpcode(Hexagon::V4_SL1_loadri_io);
+ Result.setOpcode(Hexagon::SL1_loadri_io);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
addOps(Result, Inst, 2);
@@ -868,29 +868,29 @@ MCInst HexagonMCInstrInfo::deriveSubInst
Absolute = Inst.getOperand(2).getExpr()->evaluateAsAbsolute(Value);
assert(Absolute);(void)Absolute;
if (Value == 0) {
- Result.setOpcode(Hexagon::V4_SS2_storebi0);
+ Result.setOpcode(Hexagon::SS2_storebi0);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 1,2 SUBInst memb($Rs + #$u4_0)=#0
} else if (Value == 1) {
- Result.setOpcode(Hexagon::V4_SS2_storebi1);
+ Result.setOpcode(Hexagon::SS2_storebi1);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 2 1,2 SUBInst memb($Rs + #$u4_0)=#1
}
case Hexagon::S2_storerb_io:
- Result.setOpcode(Hexagon::V4_SS1_storeb_io);
+ Result.setOpcode(Hexagon::SS1_storeb_io);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
addOps(Result, Inst, 2);
break; // 1,2,3 SUBInst memb($Rs + #$u4_0) = $Rt
case Hexagon::S2_storerd_io:
- Result.setOpcode(Hexagon::V4_SS2_stored_sp);
+ Result.setOpcode(Hexagon::SS2_stored_sp);
addOps(Result, Inst, 1);
addOps(Result, Inst, 2);
break; // 2,3 SUBInst memd(r29 + #$s6_3) = $Rtt
case Hexagon::S2_storerh_io:
- Result.setOpcode(Hexagon::V4_SS2_storeh_io);
+ Result.setOpcode(Hexagon::SS2_storeh_io);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
addOps(Result, Inst, 2);
@@ -899,88 +899,88 @@ MCInst HexagonMCInstrInfo::deriveSubInst
Absolute = Inst.getOperand(2).getExpr()->evaluateAsAbsolute(Value);
assert(Absolute);(void)Absolute;
if (Value == 0) {
- Result.setOpcode(Hexagon::V4_SS2_storewi0);
+ Result.setOpcode(Hexagon::SS2_storewi0);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 3 1,2 SUBInst memw($Rs + #$u4_2)=#0
} else if (Value == 1) {
- Result.setOpcode(Hexagon::V4_SS2_storewi1);
+ Result.setOpcode(Hexagon::SS2_storewi1);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 3 1,2 SUBInst memw($Rs + #$u4_2)=#1
} else if (Inst.getOperand(0).getReg() == Hexagon::R29) {
- Result.setOpcode(Hexagon::V4_SS2_storew_sp);
+ Result.setOpcode(Hexagon::SS2_storew_sp);
addOps(Result, Inst, 1);
addOps(Result, Inst, 2);
break; // 1 2,3 SUBInst memw(r29 + #$u5_2) = $Rt
}
case Hexagon::S2_storeri_io:
if (Inst.getOperand(0).getReg() == Hexagon::R29) {
- Result.setOpcode(Hexagon::V4_SS2_storew_sp);
+ Result.setOpcode(Hexagon::SS2_storew_sp);
addOps(Result, Inst, 1);
addOps(Result, Inst, 2); // 1,2,3 SUBInst memw(sp + #$u5_2) = $Rt
} else {
- Result.setOpcode(Hexagon::V4_SS1_storew_io);
+ Result.setOpcode(Hexagon::SS1_storew_io);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
addOps(Result, Inst, 2); // 1,2,3 SUBInst memw($Rs + #$u4_2) = $Rt
}
break;
case Hexagon::A2_sxtb:
- Result.setOpcode(Hexagon::V4_SA1_sxtb);
+ Result.setOpcode(Hexagon::SA1_sxtb);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 1,2 SUBInst $Rd = sxtb($Rs)
case Hexagon::A2_sxth:
- Result.setOpcode(Hexagon::V4_SA1_sxth);
+ Result.setOpcode(Hexagon::SA1_sxth);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 1,2 SUBInst $Rd = sxth($Rs)
case Hexagon::A2_tfr:
- Result.setOpcode(Hexagon::V4_SA1_tfr);
+ Result.setOpcode(Hexagon::SA1_tfr);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 1,2 SUBInst $Rd = $Rs
case Hexagon::C2_cmovenewif:
- Result.setOpcode(Hexagon::V4_SA1_clrfnew);
+ Result.setOpcode(Hexagon::SA1_clrfnew);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 2 SUBInst if (!p0.new) $Rd = #0
case Hexagon::C2_cmovenewit:
- Result.setOpcode(Hexagon::V4_SA1_clrtnew);
+ Result.setOpcode(Hexagon::SA1_clrtnew);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 2 SUBInst if (p0.new) $Rd = #0
case Hexagon::C2_cmoveif:
- Result.setOpcode(Hexagon::V4_SA1_clrf);
+ Result.setOpcode(Hexagon::SA1_clrf);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 2 SUBInst if (!p0) $Rd = #0
case Hexagon::C2_cmoveit:
- Result.setOpcode(Hexagon::V4_SA1_clrt);
+ Result.setOpcode(Hexagon::SA1_clrt);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 2 SUBInst if (p0) $Rd = #0
case Hexagon::A2_tfrsi:
Absolute = Inst.getOperand(1).getExpr()->evaluateAsAbsolute(Value);
if (Absolute && Value == -1) {
- Result.setOpcode(Hexagon::V4_SA1_setin1);
+ Result.setOpcode(Hexagon::SA1_setin1);
addOps(Result, Inst, 0);
break; // 2 1 SUBInst $Rd = #-1
} else {
- Result.setOpcode(Hexagon::V4_SA1_seti);
+ Result.setOpcode(Hexagon::SA1_seti);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 1,2 SUBInst $Rd = #$u6
}
case Hexagon::A2_zxtb:
- Result.setOpcode(Hexagon::V4_SA1_zxtb);
+ Result.setOpcode(Hexagon::SA1_zxtb);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 1,2 $Rd = and($Rs, #255)
case Hexagon::A2_zxth:
- Result.setOpcode(Hexagon::V4_SA1_zxth);
+ Result.setOpcode(Hexagon::SA1_zxth);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 1,2 SUBInst $Rd = zxth($Rs)
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp?rev=283514&r1=283513&r2=283514&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp Thu Oct 6 19:15:07 2016
@@ -602,58 +602,58 @@ bool HexagonMCInstrInfo::isSubInstructio
switch (MCI.getOpcode()) {
default:
return false;
- case Hexagon::V4_SA1_addi:
- case Hexagon::V4_SA1_addrx:
- case Hexagon::V4_SA1_addsp:
- case Hexagon::V4_SA1_and1:
- case Hexagon::V4_SA1_clrf:
- case Hexagon::V4_SA1_clrfnew:
- case Hexagon::V4_SA1_clrt:
- case Hexagon::V4_SA1_clrtnew:
- case Hexagon::V4_SA1_cmpeqi:
- case Hexagon::V4_SA1_combine0i:
- case Hexagon::V4_SA1_combine1i:
- case Hexagon::V4_SA1_combine2i:
- case Hexagon::V4_SA1_combine3i:
- case Hexagon::V4_SA1_combinerz:
- case Hexagon::V4_SA1_combinezr:
- case Hexagon::V4_SA1_dec:
- case Hexagon::V4_SA1_inc:
- case Hexagon::V4_SA1_seti:
- case Hexagon::V4_SA1_setin1:
- case Hexagon::V4_SA1_sxtb:
- case Hexagon::V4_SA1_sxth:
- case Hexagon::V4_SA1_tfr:
- case Hexagon::V4_SA1_zxtb:
- case Hexagon::V4_SA1_zxth:
- case Hexagon::V4_SL1_loadri_io:
- case Hexagon::V4_SL1_loadrub_io:
- case Hexagon::V4_SL2_deallocframe:
- case Hexagon::V4_SL2_jumpr31:
- case Hexagon::V4_SL2_jumpr31_f:
- case Hexagon::V4_SL2_jumpr31_fnew:
- case Hexagon::V4_SL2_jumpr31_t:
- case Hexagon::V4_SL2_jumpr31_tnew:
- case Hexagon::V4_SL2_loadrb_io:
- case Hexagon::V4_SL2_loadrd_sp:
- case Hexagon::V4_SL2_loadrh_io:
- case Hexagon::V4_SL2_loadri_sp:
- case Hexagon::V4_SL2_loadruh_io:
- case Hexagon::V4_SL2_return:
- case Hexagon::V4_SL2_return_f:
- case Hexagon::V4_SL2_return_fnew:
- case Hexagon::V4_SL2_return_t:
- case Hexagon::V4_SL2_return_tnew:
- case Hexagon::V4_SS1_storeb_io:
- case Hexagon::V4_SS1_storew_io:
- case Hexagon::V4_SS2_allocframe:
- case Hexagon::V4_SS2_storebi0:
- case Hexagon::V4_SS2_storebi1:
- case Hexagon::V4_SS2_stored_sp:
- case Hexagon::V4_SS2_storeh_io:
- case Hexagon::V4_SS2_storew_sp:
- case Hexagon::V4_SS2_storewi0:
- case Hexagon::V4_SS2_storewi1:
+ case Hexagon::SA1_addi:
+ case Hexagon::SA1_addrx:
+ case Hexagon::SA1_addsp:
+ case Hexagon::SA1_and1:
+ case Hexagon::SA1_clrf:
+ case Hexagon::SA1_clrfnew:
+ case Hexagon::SA1_clrt:
+ case Hexagon::SA1_clrtnew:
+ case Hexagon::SA1_cmpeqi:
+ case Hexagon::SA1_combine0i:
+ case Hexagon::SA1_combine1i:
+ case Hexagon::SA1_combine2i:
+ case Hexagon::SA1_combine3i:
+ case Hexagon::SA1_combinerz:
+ case Hexagon::SA1_combinezr:
+ case Hexagon::SA1_dec:
+ case Hexagon::SA1_inc:
+ case Hexagon::SA1_seti:
+ case Hexagon::SA1_setin1:
+ case Hexagon::SA1_sxtb:
+ case Hexagon::SA1_sxth:
+ case Hexagon::SA1_tfr:
+ case Hexagon::SA1_zxtb:
+ case Hexagon::SA1_zxth:
+ case Hexagon::SL1_loadri_io:
+ case Hexagon::SL1_loadrub_io:
+ case Hexagon::SL2_deallocframe:
+ case Hexagon::SL2_jumpr31:
+ case Hexagon::SL2_jumpr31_f:
+ case Hexagon::SL2_jumpr31_fnew:
+ case Hexagon::SL2_jumpr31_t:
+ case Hexagon::SL2_jumpr31_tnew:
+ case Hexagon::SL2_loadrb_io:
+ case Hexagon::SL2_loadrd_sp:
+ case Hexagon::SL2_loadrh_io:
+ case Hexagon::SL2_loadri_sp:
+ case Hexagon::SL2_loadruh_io:
+ case Hexagon::SL2_return:
+ case Hexagon::SL2_return_f:
+ case Hexagon::SL2_return_fnew:
+ case Hexagon::SL2_return_t:
+ case Hexagon::SL2_return_tnew:
+ case Hexagon::SS1_storeb_io:
+ case Hexagon::SS1_storew_io:
+ case Hexagon::SS2_allocframe:
+ case Hexagon::SS2_storebi0:
+ case Hexagon::SS2_storebi1:
+ case Hexagon::SS2_stored_sp:
+ case Hexagon::SS2_storeh_io:
+ case Hexagon::SS2_storew_sp:
+ case Hexagon::SS2_storewi0:
+ case Hexagon::SS2_storewi1:
return true;
}
}
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