[PATCH] D25312: AMDGPU: Fix use-after-frees

[Justin Bogner via llvm-commits]

Nicolai Hähnle via llvm-commits <llvm-commits at lists.llvm.org> writes:
> nhaehnle created this revision.
> nhaehnle added reviewers: arsenm, tstellarAMD.
> nhaehnle added a subscriber: llvm-commits.
> Herald added subscribers: tony-tye, yaxunl, wdng, kzhuravl.
>
> https://reviews.llvm.org/D25312

LGTM.

> Files:
>   lib/Target/AMDGPU/SIISelLowering.cpp
>   lib/Target/AMDGPU/SIRegisterInfo.cpp
>
>
> Index: lib/Target/AMDGPU/SIRegisterInfo.cpp
> ===================================================================
> --- lib/Target/AMDGPU/SIRegisterInfo.cpp
> +++ lib/Target/AMDGPU/SIRegisterInfo.cpp
> @@ -611,8 +611,8 @@
>              TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)->getReg(),
>              FrameInfo.getObjectOffset(Index) +
>              TII->getNamedOperand(*MI, AMDGPU::OpName::offset)->getImm(), RS);
> -      MI->eraseFromParent();
>        MFI->addToSpilledVGPRs(getNumSubRegsForSpillOp(MI->getOpcode()));
> +      MI->eraseFromParent();
>        break;
>      case AMDGPU::SI_SPILL_V32_RESTORE:
>      case AMDGPU::SI_SPILL_V64_RESTORE:
> Index: lib/Target/AMDGPU/SIISelLowering.cpp
> ===================================================================
> --- lib/Target/AMDGPU/SIISelLowering.cpp
> +++ lib/Target/AMDGPU/SIISelLowering.cpp
> @@ -1305,28 +1305,28 @@
>    MachineRegisterInfo &MRI = MF->getRegInfo();
>  
>    unsigned Dst = MI.getOperand(0).getReg();
> -  const MachineOperand *SrcVec = TII->getNamedOperand(MI, AMDGPU::OpName::src);
> +  unsigned SrcReg = TII->getNamedOperand(MI, AMDGPU::OpName::src)->getReg();
>    int Offset = TII->getNamedOperand(MI, AMDGPU::OpName::offset)->getImm();
>  
> -  const TargetRegisterClass *VecRC = MRI.getRegClass(SrcVec->getReg());
> +  const TargetRegisterClass *VecRC = MRI.getRegClass(SrcReg);
>  
>    unsigned SubReg;
>    std::tie(SubReg, Offset)
> -    = computeIndirectRegAndOffset(TRI, VecRC, SrcVec->getReg(), Offset);
> +    = computeIndirectRegAndOffset(TRI, VecRC, SrcReg, Offset);
>  
>    if (setM0ToIndexFromSGPR(TII, MRI, MI, Offset)) {
>      MachineBasicBlock::iterator I(&MI);
>      const DebugLoc &DL = MI.getDebugLoc();
>  
>      BuildMI(MBB, I, DL, TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst)
> -      .addReg(SrcVec->getReg(), RegState::Undef, SubReg)
> -      .addReg(SrcVec->getReg(), RegState::Implicit);
> +      .addReg(SrcReg, RegState::Undef, SubReg)
> +      .addReg(SrcReg, RegState::Implicit);
>      MI.eraseFromParent();
>  
>      return &MBB;
>    }
>  
> -  const DebugLoc &DL = MI.getDebugLoc();
> +  const DebugLoc DL = MI.getDebugLoc();
>    MachineBasicBlock::iterator I(&MI);
>  
>    unsigned PhiReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
> @@ -1339,8 +1339,8 @@
>  
>    BuildMI(*InsPt->getParent(), InsPt, DL,
>            TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst)
> -    .addReg(SrcVec->getReg(), RegState::Undef, SubReg)
> -    .addReg(SrcVec->getReg(), RegState::Implicit);
> +    .addReg(SrcReg, RegState::Undef, SubReg)
> +    .addReg(SrcReg, RegState::Implicit);
>  
>    return InsPt->getParent();
>  }
> @@ -1406,7 +1406,7 @@
>    if (Val->isReg())
>      MRI.clearKillFlags(Val->getReg());
>  
> -  const DebugLoc &DL = MI.getDebugLoc();
> +  const DebugLoc DL = MI.getDebugLoc();
>    unsigned PhiReg = MRI.createVirtualRegister(VecRC);
>  
>    auto InsPt = loadM0FromVGPR(TII, MBB, MI, SrcVec->getReg(), PhiReg, Offset);
>
>
> Index: lib/Target/AMDGPU/SIRegisterInfo.cpp
> ===================================================================
> --- lib/Target/AMDGPU/SIRegisterInfo.cpp
> +++ lib/Target/AMDGPU/SIRegisterInfo.cpp
> @@ -611,8 +611,8 @@
>              TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)->getReg(),
>              FrameInfo.getObjectOffset(Index) +
>              TII->getNamedOperand(*MI, AMDGPU::OpName::offset)->getImm(), RS);
> -      MI->eraseFromParent();
>        MFI->addToSpilledVGPRs(getNumSubRegsForSpillOp(MI->getOpcode()));
> +      MI->eraseFromParent();
>        break;
>      case AMDGPU::SI_SPILL_V32_RESTORE:
>      case AMDGPU::SI_SPILL_V64_RESTORE:
> Index: lib/Target/AMDGPU/SIISelLowering.cpp
> ===================================================================
> --- lib/Target/AMDGPU/SIISelLowering.cpp
> +++ lib/Target/AMDGPU/SIISelLowering.cpp
> @@ -1305,28 +1305,28 @@
>    MachineRegisterInfo &MRI = MF->getRegInfo();
>  
>    unsigned Dst = MI.getOperand(0).getReg();
> -  const MachineOperand *SrcVec = TII->getNamedOperand(MI, AMDGPU::OpName::src);
> +  unsigned SrcReg = TII->getNamedOperand(MI, AMDGPU::OpName::src)->getReg();
>    int Offset = TII->getNamedOperand(MI, AMDGPU::OpName::offset)->getImm();
>  
> -  const TargetRegisterClass *VecRC = MRI.getRegClass(SrcVec->getReg());
> +  const TargetRegisterClass *VecRC = MRI.getRegClass(SrcReg);
>  
>    unsigned SubReg;
>    std::tie(SubReg, Offset)
> -    = computeIndirectRegAndOffset(TRI, VecRC, SrcVec->getReg(), Offset);
> +    = computeIndirectRegAndOffset(TRI, VecRC, SrcReg, Offset);
>  
>    if (setM0ToIndexFromSGPR(TII, MRI, MI, Offset)) {
>      MachineBasicBlock::iterator I(&MI);
>      const DebugLoc &DL = MI.getDebugLoc();
>  
>      BuildMI(MBB, I, DL, TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst)
> -      .addReg(SrcVec->getReg(), RegState::Undef, SubReg)
> -      .addReg(SrcVec->getReg(), RegState::Implicit);
> +      .addReg(SrcReg, RegState::Undef, SubReg)
> +      .addReg(SrcReg, RegState::Implicit);
>      MI.eraseFromParent();
>  
>      return &MBB;
>    }
>  
> -  const DebugLoc &DL = MI.getDebugLoc();
> +  const DebugLoc DL = MI.getDebugLoc();
>    MachineBasicBlock::iterator I(&MI);
>  
>    unsigned PhiReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
> @@ -1339,8 +1339,8 @@
>  
>    BuildMI(*InsPt->getParent(), InsPt, DL,
>            TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst)
> -    .addReg(SrcVec->getReg(), RegState::Undef, SubReg)
> -    .addReg(SrcVec->getReg(), RegState::Implicit);
> +    .addReg(SrcReg, RegState::Undef, SubReg)
> +    .addReg(SrcReg, RegState::Implicit);
>  
>    return InsPt->getParent();
>  }
> @@ -1406,7 +1406,7 @@
>    if (Val->isReg())
>      MRI.clearKillFlags(Val->getReg());
>  
> -  const DebugLoc &DL = MI.getDebugLoc();
> +  const DebugLoc DL = MI.getDebugLoc();
>    unsigned PhiReg = MRI.createVirtualRegister(VecRC);
>  
>    auto InsPt = loadM0FromVGPR(TII, MBB, MI, SrcVec->getReg(), PhiReg, Offset);
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