[PATCH] D25268: Handle *_EXTEND_VECTOR_INREG during Integer Legalization

[Pirama Arumuga Nainar via llvm-commits]

pirama added inline comments.


> RKSimon wrote in LegalizeIntegerTypes.cpp:3355
> Are you sure we're correctly handling the extension in this case? Promotion tends to leave the upper bits as garbage - won't we still need to perform a SIGN_EXTEND_INREG/ZERO_EXTEND_INREG.

Aah, that's right.  I couldn't craft a test IR where an EXTEND_VECTOR_INREG gets generated by DAGCombine that matches the actual TransformTo type.  Maybe this is infeasible.  I'll remove this separate handling.

> RKSimon wrote in promote-vec3.ll:1
> Please use an -mattr=+ssse3 instead of a specific cpu target. Also test for SSE4.1 / AVX / AVX2 cases as well if you can, even though these probably don't use this new code path - just to check codegen.
> 
> Also please regenerate with utils\update_llc_test_checks.py

'll add your suggested changes to this test.

I ran update_llc_test_checks and the checks seem to hard-code registers.  Is this fine?  (I've had issues in the past where hard-coded register values cause test failures on some bots where the RA picked a different set of registers).

https://reviews.llvm.org/D25268