[llvm] r283326 - [X86] Don't randomly encode %rip where illegal
Douglas Katzman via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 5 08:23:36 PDT 2016
Author: dougk
Date: Wed Oct 5 10:23:35 2016
New Revision: 283326
URL: http://llvm.org/viewvc/llvm-project?rev=283326&view=rev
Log:
[X86] Don't randomly encode %rip where illegal
Differential Revision: https://reviews.llvm.org/D25112
Modified:
llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp
llvm/trunk/lib/Target/X86/X86RegisterInfo.td
llvm/trunk/test/MC/X86/intel-syntax-error.s
llvm/trunk/test/MC/X86/x86_errors.s
Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=283326&r1=283325&r2=283326&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original)
+++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Wed Oct 5 10:23:35 2016
@@ -840,6 +840,11 @@ static bool CheckBaseRegAndIndexReg(unsi
// If we have both a base register and an index register make sure they are
// both 64-bit or 32-bit registers.
// To support VSIB, IndexReg can be 128-bit or 256-bit registers.
+
+ if ((BaseReg == X86::RIP && IndexReg != 0) || (IndexReg == X86::RIP)) {
+ ErrMsg = "invalid base+index expression";
+ return true;
+ }
if (BaseReg != 0 && IndexReg != 0) {
if (X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg) &&
(X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
@@ -1781,10 +1786,12 @@ std::unique_ptr<X86Operand> X86AsmParser
!ParseRegister(RegNo, Start, End)) {
// If this is a segment register followed by a ':', then this is the start
// of a segment override, otherwise this is a normal register reference.
- // In case it is a normal register and there is ptr in the operand this
+ // In case it is a normal register and there is ptr in the operand this
// is an error
- if (getLexer().isNot(AsmToken::Colon)){
- if (PtrInOperand){
+ if (RegNo == X86::RIP)
+ return ErrorOperand(Start, "rip can only be used as a base register");
+ if (getLexer().isNot(AsmToken::Colon)) {
+ if (PtrInOperand) {
return ErrorOperand(Start, "expected memory operand after "
"'ptr', found register operand instead");
}
@@ -1865,6 +1872,11 @@ std::unique_ptr<X86Operand> X86AsmParser
SMRange(Start, End));
return nullptr;
}
+ if (RegNo == X86::RIP) {
+ Error(Start, "%rip can only be used as a base register",
+ SMRange(Start, End));
+ return nullptr;
+ }
// If this is a segment register followed by a ':', then this is the start
// of a memory reference, otherwise this is a normal register reference.
@@ -2044,7 +2056,16 @@ std::unique_ptr<X86Operand> X86AsmParser
// like "1(%eax,,1)", the assembler doesn't. Use "eiz" or "riz" for this.
if (getLexer().is(AsmToken::Percent)) {
SMLoc L;
- if (ParseRegister(IndexReg, L, L)) return nullptr;
+ if (ParseRegister(IndexReg, L, L))
+ return nullptr;
+ if (BaseReg == X86::RIP) {
+ Error(IndexLoc, "%rip as base register can not have an index register");
+ return nullptr;
+ }
+ if (IndexReg == X86::RIP) {
+ Error(IndexLoc, "%rip is not allowed as an index register");
+ return nullptr;
+ }
if (getLexer().isNot(AsmToken::RParen)) {
// Parse the scale amount:
Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.td?rev=283326&r1=283325&r2=283326&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.td Wed Oct 5 10:23:35 2016
@@ -345,6 +345,8 @@ def GR32 : RegisterClass<"X86", [i32], 3
// GR64 - 64-bit GPRs. This oddly includes RIP, which isn't accurate, since
// RIP isn't really a register and it can't be used anywhere except in an
// address, but it doesn't cause trouble.
+// FIXME: it *does* cause trouble - CheckBaseRegAndIndexReg() has extra
+// tests because of the inclusion of RIP in this register class.
def GR64 : RegisterClass<"X86", [i64], 64,
(add RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
RBX, R14, R15, R12, R13, RBP, RSP, RIP)>;
Modified: llvm/trunk/test/MC/X86/intel-syntax-error.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/intel-syntax-error.s?rev=283326&r1=283325&r2=283326&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/intel-syntax-error.s (original)
+++ llvm/trunk/test/MC/X86/intel-syntax-error.s Wed Oct 5 10:23:35 2016
@@ -24,3 +24,8 @@ mov eax, DWORD PTR arr[ebp + 1 + (2 * 5)
mov eax, DWORD PTR arr[esi*4]
//CHECK: error: cannot use more than one symbol in memory operand
mov eax, DWORD PTR arr[i]
+//CHECK: error: rip can only be used as a base register
+.code64
+mov rax, rip
+//CHECK: error: invalid base+index expression
+mov rbx, [rax+rip]
Modified: llvm/trunk/test/MC/X86/x86_errors.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86_errors.s?rev=283326&r1=283325&r2=283326&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/x86_errors.s (original)
+++ llvm/trunk/test/MC/X86/x86_errors.s Wed Oct 5 10:23:35 2016
@@ -74,3 +74,11 @@ movl %edx, %cr8
// 32: error: register %dr8 is only available in 64-bit mode
movl %edx, %dr8
+
+// 32: error: register %rip is only available in 64-bit mode
+// 64: error: %rip can only be used as a base register
+mov %rip, %rax
+
+// 32: error: register %rax is only available in 64-bit mode
+// 64: error: %rip is not allowed as an index register
+mov (%rax,%rip), %rbx
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