[llvm] r283315 - Fix machine operand traversal in ScheduleDAGInstrs::fixupKills

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Wed Oct  5 08:15:06 2016
New Revision: 283315

URL: http://llvm.org/viewvc/llvm-project?rev=283315&view=rev
Log:
Fix machine operand traversal in ScheduleDAGInstrs::fixupKills

Added:
    llvm/trunk/test/CodeGen/Hexagon/post-ra-kill-update.mir
Modified:
    llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp

Modified: llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp?rev=283315&r1=283314&r2=283315&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp (original)
+++ llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp Wed Oct  5 08:15:06 2016
@@ -1309,7 +1309,13 @@ void ScheduleDAGInstrs::fixupKills(Machi
     // register is used multiple times we only set the kill flag on
     // the first use. Don't set kill flags on undef operands.
     killedRegs.reset();
-    for (MachineOperand &MO : MI.operands()) {
+
+    // toggleKillFlag can append new operands (implicit defs), so using
+    // a range-based loop is not safe. The new operands will be appended
+    // at the end of the operand list and they don't need to be visited,
+    // so iterating until the currently last operand is ok.
+    for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
+      MachineOperand &MO = MI.getOperand(i);
       if (!MO.isReg() || !MO.isUse() || MO.isUndef()) continue;
       unsigned Reg = MO.getReg();
       if ((Reg == 0) || MRI.isReserved(Reg)) continue;
@@ -1333,7 +1339,6 @@ void ScheduleDAGInstrs::fixupKills(Machi
 
       if (MO.isKill() != kill) {
         DEBUG(dbgs() << "Fixing " << MO << " in ");
-        // Warning: toggleKillFlag may invalidate MO.
         toggleKillFlag(&MI, MO);
         DEBUG(MI.dump());
         DEBUG({

Added: llvm/trunk/test/CodeGen/Hexagon/post-ra-kill-update.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/post-ra-kill-update.mir?rev=283315&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/post-ra-kill-update.mir (added)
+++ llvm/trunk/test/CodeGen/Hexagon/post-ra-kill-update.mir Wed Oct  5 08:15:06 2016
@@ -0,0 +1,37 @@
+# RUN: llc -march=hexagon -mcpu=hexagonv60 -run-pass post-RA-sched -o - %s | FileCheck %s
+
+# The post-RA scheduler reorders S2_lsr_r_p and S2_lsr_r_p_or. Both of them
+# use r9, and the last of the two kills it. The kill flag fixup did not
+# correctly update the flag, resulting in both instructions killing r9.
+
+# CHECK-LABEL: name: foo
+# Check for no-kill of r9 in the first instruction, after reordering:
+# CHECK: %d7 = S2_lsr_r_p_or %d7, killed %d1, %r9
+# CHECK: %d13 = S2_lsr_r_p killed %d0, killed %r9
+
+--- |
+  define void @foo() {
+    ret void
+  }
+...
+
+---
+name: foo
+tracksRegLiveness: true
+body: |
+  bb.0:
+    successors: %bb.1
+    liveins: %d0, %d1, %r9, %r13
+
+    %d7 = S2_asl_r_p %d0, %r13
+    %d5 = S2_asl_r_p %d1, killed %r13
+    %d6 = S2_lsr_r_p killed %d0, %r9
+    %d7 = S2_lsr_r_p_or killed %d7, killed %d1, killed %r9
+    %d1 = A2_combinew killed %r11, killed %r10
+    %d0 = A2_combinew killed %r15, killed %r14
+    J2_jump %bb.1, implicit-def %pc
+
+  bb.1:
+    A2_nop
+...
+