[PATCH] D25268: Handle *_EXTEND_VECTOR_INREG during Integer Legalization

[Pirama Arumuga Nainar via llvm-commits]

pirama created this revision.
pirama added reviewers: RKSimon, srhines.
pirama added a subscriber: llvm-commits.

These nodes need legalization for 3-element vectors.  This commit
handles the legalization and adds tests for zext and sext.

This fixes PR30614.


https://reviews.llvm.org/D25268

Files:
  lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  lib/CodeGen/SelectionDAG/LegalizeTypes.h
  test/CodeGen/X86/promote-vec3.ll


Index: test/CodeGen/X86/promote-vec3.ll
===================================================================
--- /dev/null
+++ test/CodeGen/X86/promote-vec3.ll
@@ -0,0 +1,21 @@
+; RUN: llc < %s -mtriple=i686-unknown-unknown -mcpu=atom | FileCheck %s
+
+; CHECK-LABEL: zext_i8:
+; CHECK-DAG: pinsrw $0
+; CHECK-DAG: pinsrw $1
+; CHECK-DAG: pinsrw $2
+; CHECK: punpcklwd
+define <3 x i16> @zext_i8(<3 x i8>) {
+  %2 = zext <3 x i8> %0 to <3 x i16>
+  ret <3 x i16> %2
+}
+
+; CHECK-LABEL: sext_i8:
+; CHECK-DAG: pinsrw $0, {{.*}}, [[XMMREG:%xmm[0-8]+]]
+; CHECK-DAG: pinsrw $1, {{.*}}, [[XMMREG]]
+; CHECK-DAG: pinsrw $2, {{.*}}, [[XMMREG]]
+; CHECK: punpcklwd [[XMMREG]], [[XMMREG]]
+define <3 x i16> @sext_i8(<3 x i8>) {
+  %2 = sext <3 x i8> %0 to <3 x i16>
+  ret <3 x i16> %2
+}
Index: lib/CodeGen/SelectionDAG/LegalizeTypes.h
===================================================================
--- lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -242,6 +242,7 @@
   SDValue PromoteIntRes_VECTOR_SHUFFLE(SDNode *N);
   SDValue PromoteIntRes_BUILD_VECTOR(SDNode *N);
   SDValue PromoteIntRes_SCALAR_TO_VECTOR(SDNode *N);
+  SDValue PromoteIntRes_EXTEND_VECTOR_INREG(SDNode *N);
   SDValue PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N);
   SDValue PromoteIntRes_CONCAT_VECTORS(SDNode *N);
   SDValue PromoteIntRes_BITCAST(SDNode *N);
Index: lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -102,6 +102,11 @@
   case ISD::CONCAT_VECTORS:
                          Res = PromoteIntRes_CONCAT_VECTORS(N); break;
 
+  case ISD::ANY_EXTEND_VECTOR_INREG:
+  case ISD::SIGN_EXTEND_VECTOR_INREG:
+  case ISD::ZERO_EXTEND_VECTOR_INREG:
+                         Res = PromoteIntRes_EXTEND_VECTOR_INREG(N); break;
+
   case ISD::SIGN_EXTEND:
   case ISD::ZERO_EXTEND:
   case ISD::ANY_EXTEND:  Res = PromoteIntRes_INT_EXTEND(N); break;
@@ -3334,6 +3339,28 @@
   return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, Ops);
 }
 
+SDValue DAGTypeLegalizer::PromoteIntRes_EXTEND_VECTOR_INREG(SDNode *N) {
+  EVT VT = N->getValueType(0);
+  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
+  assert(NVT.isVector() && "This type must be promoted to a vector type");
+
+  SDLoc dl(N);
+
+  // For operands whose TypeAction is to promote, either reuse the promoted node
+  // if it is already the correct type or use the promoted node to construct
+  // a new *_EXTEND_VECTOR_INREG node.
+  if (getTypeAction(N->getOperand(0).getValueType())
+      == TargetLowering::TypePromoteInteger) {
+    SDValue Promoted = GetPromotedInteger(N->getOperand(0));
+    if (Promoted.getValueType() == NVT)
+      return Promoted;
+    return DAG.getNode(N->getOpcode(), dl, NVT, Promoted);
+  }
+
+  // Directly extend to the appropriate transform-to type.
+  return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
+}
+
 SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N) {
   EVT OutVT = N->getValueType(0);
   EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);


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