[PATCH] D23446: [X86] Enable setcc to srl(ctlz) transformation on btver2 architectures.

[pierre gousseau via llvm-commits]

pgousseau updated this revision to Diff 73497.
pgousseau added a comment.

Hi Simon/Sanjay,

Following up with with the previous comments, this patch contains:

- Use of DAG.getZextOrTrunc as per Simon's comment.
- Removed support for the simple case.
- Added handling of OR based patterns.
- Added a case for SRL nodes in 'isTypeDesirableForOp()' as to favor 32 bits encoding when targetting X86.
- Added support for multiple OR patterns eg: (a1||a2||a3||a4||a5)

Let me know what you think,

Thanks!


https://reviews.llvm.org/D23446

Files:
  include/llvm/Target/TargetLowering.h
  lib/CodeGen/SelectionDAG/TargetLowering.cpp
  lib/Target/PowerPC/PPCISelLowering.cpp
  lib/Target/X86/X86.td
  lib/Target/X86/X86ISelLowering.cpp
  lib/Target/X86/X86ISelLowering.h
  lib/Target/X86/X86InstrInfo.td
  lib/Target/X86/X86Subtarget.cpp
  lib/Target/X86/X86Subtarget.h
  test/CodeGen/X86/lzcnt-zext-cmp.ll

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