[llvm] r283130 - [AMDGPU] Sign extend AShr when promoting (instead of zero extending)

[Konstantin Zhuravlyov via llvm-commits]

Author: kzhuravl
Date: Mon Oct  3 13:29:01 2016
New Revision: 283130

URL: http://llvm.org/viewvc/llvm-project?rev=283130&view=rev
Log:
[AMDGPU] Sign extend AShr when promoting (instead of zero extending)

Modified:
    llvm/trunk/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
    llvm/trunk/test/CodeGen/AMDGPU/amdgpu-codegenprepare-i16-to-i32.ll

Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp?rev=283130&r1=283129&r2=283130&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp Mon Oct  3 13:29:01 2016
@@ -172,8 +172,8 @@ bool AMDGPUCodeGenPrepare::isI32Ty(const
 }
 
 bool AMDGPUCodeGenPrepare::isSigned(const BinaryOperator &I) const {
-  return I.getOpcode() == Instruction::SDiv ||
-      I.getOpcode() == Instruction::SRem;
+  return I.getOpcode() == Instruction::AShr ||
+      I.getOpcode() == Instruction::SDiv || I.getOpcode() == Instruction::SRem;
 }
 
 bool AMDGPUCodeGenPrepare::isSigned(const SelectInst &I) const {

Modified: llvm/trunk/test/CodeGen/AMDGPU/amdgpu-codegenprepare-i16-to-i32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/amdgpu-codegenprepare-i16-to-i32.ll?rev=283130&r1=283129&r2=283130&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/amdgpu-codegenprepare-i16-to-i32.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/amdgpu-codegenprepare-i16-to-i32.ll Mon Oct  3 13:29:01 2016
@@ -226,8 +226,8 @@ define i16 @lshr_exact_i16(i16 %a, i16 %
 }
 
 ; VI-LABEL: @ashr_i16(
-; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32
-; VI: %[[B_32:[0-9]+]] = zext i16 %b to i32
+; VI: %[[A_32:[0-9]+]] = sext i16 %a to i32
+; VI: %[[B_32:[0-9]+]] = sext i16 %b to i32
 ; VI: %[[R_32:[0-9]+]] = ashr i32 %[[A_32]], %[[B_32]]
 ; VI: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16
 ; VI: ret i16 %[[R_16]]
@@ -237,8 +237,8 @@ define i16 @ashr_i16(i16 %a, i16 %b) {
 }
 
 ; VI-LABEL: @ashr_exact_i16(
-; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32
-; VI: %[[B_32:[0-9]+]] = zext i16 %b to i32
+; VI: %[[A_32:[0-9]+]] = sext i16 %a to i32
+; VI: %[[B_32:[0-9]+]] = sext i16 %b to i32
 ; VI: %[[R_32:[0-9]+]] = ashr exact i32 %[[A_32]], %[[B_32]]
 ; VI: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16
 ; VI: ret i16 %[[R_16]]
@@ -651,8 +651,8 @@ define <3 x i16> @lshr_exact_3xi16(<3 x
 }
 
 ; VI-LABEL: @ashr_3xi16(
-; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32>
-; VI: %[[B_32:[0-9]+]] = zext <3 x i16> %b to <3 x i32>
+; VI: %[[A_32:[0-9]+]] = sext <3 x i16> %a to <3 x i32>
+; VI: %[[B_32:[0-9]+]] = sext <3 x i16> %b to <3 x i32>
 ; VI: %[[R_32:[0-9]+]] = ashr <3 x i32> %[[A_32]], %[[B_32]]
 ; VI: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16>
 ; VI: ret <3 x i16> %[[R_16]]
@@ -662,8 +662,8 @@ define <3 x i16> @ashr_3xi16(<3 x i16> %
 }
 
 ; VI-LABEL: @ashr_exact_3xi16(
-; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32>
-; VI: %[[B_32:[0-9]+]] = zext <3 x i16> %b to <3 x i32>
+; VI: %[[A_32:[0-9]+]] = sext <3 x i16> %a to <3 x i32>
+; VI: %[[B_32:[0-9]+]] = sext <3 x i16> %b to <3 x i32>
 ; VI: %[[R_32:[0-9]+]] = ashr exact <3 x i32> %[[A_32]], %[[B_32]]
 ; VI: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16>
 ; VI: ret <3 x i16> %[[R_16]]