[PATCH] D25165: [x86] allow 128/256-bit lowering for copysign vector intrinsics (PR30433)

[Sanjay Patel via llvm-commits]

spatel added a comment.

In https://reviews.llvm.org/D25165#558579, @zvi wrote:

> LGTM.
>  Note that since sign-mask and mag-mask are complementary, we could avoid one constant-pool load with ANDNPS.


Thanks, Zvi. I thought about that, but this is a general problem: AFAIK, we just don't have very good constant combining/hoisting logic in the backend. I noticed this recently in:
https://llvm.org/bugs/show_bug.cgi?id=28672#c3

Also, see:
https://llvm.org/bugs/show_bug.cgi?id=25554
https://llvm.org/bugs/show_bug.cgi?id=24448
https://llvm.org/bugs/show_bug.cgi?id=27202

It seems like constant combining at the machine level could be its own pass, so we shouldn't have to special-case situations like this one.


https://reviews.llvm.org/D25165