[PATCH] D25181: AMDGPU: Add definitions for scalar store instructions

[Matt Arsenault via llvm-commits]

arsenm created this revision.
arsenm added a reviewer: tstellarAMD.
arsenm added a subscriber: llvm-commits.
Herald added subscribers: tony-tye, yaxunl, nhaehnle, wdng, kzhuravl.

Also add glc bit to the scalar loads since they exist on VI
and change the caching behavior.

      

This currently has an assembler bug where the glc bit is incorrectly
accepted on SI/CI which do not have it.


https://reviews.llvm.org/D25181

Files:
  lib/Target/AMDGPU/AMDGPU.td
  lib/Target/AMDGPU/AMDGPUSubtarget.h
  lib/Target/AMDGPU/SMInstructions.td
  test/CodeGen/AMDGPU/coalescer-subreg-join.mir
  test/MC/AMDGPU/smem.s
  test/MC/AMDGPU/smrd-err.s

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