[PATCH] D25180: [ARM] Fix registers clobbered by SjLj EH on soft-float targets

[Oliver Stannard via llvm-commits]

olista01 created this revision.
olista01 added a reviewer: t.p.northover.
olista01 added a subscriber: llvm-commits.
olista01 set the repository for this revision to rL LLVM.
Herald added subscribers: samparker, rengolin, aemerson.

Currently, the Int_eh_sjlj_dispatchsetup intrinsic is marked as
clobbering all registers, including floating-point registers that may
not be present on the target. This is technically true, as we could get
linked against code that does use the FP registers, but that will not
actually work, as the soft-float code cannot save and restore the FP
registers. SjLj exception handling can only work correctly if either all
or none of the code is built for a target with FP registers. Therefore,
we can assume that, when Int_eh_sjlj_dispatchsetup is compiled for a
soft-float target, it is only going to be linked against other
soft-float code, and so only clobbers the general-purpose registers.
This allows us to check that no non-savable registers are clobbered when
generating the prologue/epilogue.


Repository:
  rL LLVM

https://reviews.llvm.org/D25180

Files:
  lib/Target/ARM/ARMBaseRegisterInfo.cpp
  lib/Target/ARM/ARMBaseRegisterInfo.h
  lib/Target/ARM/ARMCallingConv.td
  lib/Target/ARM/ARMISelLowering.cpp
  test/CodeGen/ARM/eh-dispcont.ll

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