[PATCH] D25176: [AMDGPU] Sign extend AShr when promoting (instead of zero extending)

[Konstantin Zhuravlyov via llvm-commits]

kzhuravl created this revision.
kzhuravl added reviewers: tstellarAMD, arsenm.
kzhuravl added a subscriber: llvm-commits.
Herald added subscribers: tony-tye, yaxunl, nhaehnle, wdng.

https://reviews.llvm.org/D25176

Files:
  lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
  test/CodeGen/AMDGPU/amdgpu-codegenprepare-i16-to-i32.ll


Index: test/CodeGen/AMDGPU/amdgpu-codegenprepare-i16-to-i32.ll
===================================================================
--- test/CodeGen/AMDGPU/amdgpu-codegenprepare-i16-to-i32.ll
+++ test/CodeGen/AMDGPU/amdgpu-codegenprepare-i16-to-i32.ll
@@ -264,8 +264,8 @@
 ; GCN-LABEL: @ashr_i16(
 ; SI: %r = ashr i16 %a, %b
 ; SI-NEXT: ret i16 %r
-; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32
-; VI-NEXT: %[[B_32:[0-9]+]] = zext i16 %b to i32
+; VI: %[[A_32:[0-9]+]] = sext i16 %a to i32
+; VI-NEXT: %[[B_32:[0-9]+]] = sext i16 %b to i32
 ; VI-NEXT: %[[R_32:[0-9]+]] = ashr i32 %[[A_32]], %[[B_32]]
 ; VI-NEXT: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16
 ; VI-NEXT: ret i16 %[[R_16]]
@@ -277,8 +277,8 @@
 ; GCN-LABEL: @ashr_exact_i16(
 ; SI: %r = ashr exact i16 %a, %b
 ; SI-NEXT: ret i16 %r
-; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32
-; VI-NEXT: %[[B_32:[0-9]+]] = zext i16 %b to i32
+; VI: %[[A_32:[0-9]+]] = sext i16 %a to i32
+; VI-NEXT: %[[B_32:[0-9]+]] = sext i16 %b to i32
 ; VI-NEXT: %[[R_32:[0-9]+]] = ashr exact i32 %[[A_32]], %[[B_32]]
 ; VI-NEXT: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16
 ; VI-NEXT: ret i16 %[[R_16]]
@@ -783,8 +783,8 @@
 ; GCN-LABEL: @ashr_3xi16(
 ; SI: %r = ashr <3 x i16> %a, %b
 ; SI-NEXT: ret <3 x i16> %r
-; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32>
-; VI-NEXT: %[[B_32:[0-9]+]] = zext <3 x i16> %b to <3 x i32>
+; VI: %[[A_32:[0-9]+]] = sext <3 x i16> %a to <3 x i32>
+; VI-NEXT: %[[B_32:[0-9]+]] = sext <3 x i16> %b to <3 x i32>
 ; VI-NEXT: %[[R_32:[0-9]+]] = ashr <3 x i32> %[[A_32]], %[[B_32]]
 ; VI-NEXT: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16>
 ; VI-NEXT: ret <3 x i16> %[[R_16]]
@@ -796,8 +796,8 @@
 ; GCN-LABEL: @ashr_exact_3xi16(
 ; SI: %r = ashr exact <3 x i16> %a, %b
 ; SI-NEXT: ret <3 x i16> %r
-; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32>
-; VI-NEXT: %[[B_32:[0-9]+]] = zext <3 x i16> %b to <3 x i32>
+; VI: %[[A_32:[0-9]+]] = sext <3 x i16> %a to <3 x i32>
+; VI-NEXT: %[[B_32:[0-9]+]] = sext <3 x i16> %b to <3 x i32>
 ; VI-NEXT: %[[R_32:[0-9]+]] = ashr exact <3 x i32> %[[A_32]], %[[B_32]]
 ; VI-NEXT: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16>
 ; VI-NEXT: ret <3 x i16> %[[R_16]]
Index: lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
===================================================================
--- lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
+++ lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
@@ -185,7 +185,7 @@
 
 bool AMDGPUCodeGenPrepare::isSigned(const BinaryOperator &I) const {
   return I.getOpcode() == Instruction::SDiv ||
-      I.getOpcode() == Instruction::SRem;
+      I.getOpcode() == Instruction::SRem || I.getOpcode() == Instruction::AShr;
 }
 
 bool AMDGPUCodeGenPrepare::isSigned(const SelectInst &I) const {


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