[PATCH] [Request, 22 lines] D25080: [AArch64] Support 16 bit FP in inline asm register selection

[Florian Hahn via llvm-commits]

fhahn created this revision.
fhahn added a reviewer: t.p.northover.
fhahn added a subscriber: llvm-commits.
Herald added subscribers: rengolin, aemerson.

https://reviews.llvm.org/D25080

Files:
  lib/Target/AArch64/AArch64ISelLowering.cpp
  test/CodeGen/AArch64/neon-inline-asm-16-bit-fp.ll


Index: test/CodeGen/AArch64/neon-inline-asm-16-bit-fp.ll
===================================================================
--- /dev/null
+++ test/CodeGen/AArch64/neon-inline-asm-16-bit-fp.ll
@@ -0,0 +1,20 @@
+; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
+
+; generated from
+; __fp16 test(__fp16 a1, __fp16 a2) {
+;    __fp16 res0;
+;    __asm__("sqrshl %h[__res], %h[__Pg], %h[__Zn]"
+;             : [__res] "=w" (res0)
+;             : [__Pg] "w" (a1), [__Zn] "w" (a1)
+;             :
+;             );
+;    return res0;
+;}
+
+; Function Attrs: nounwind readnone
+define half @test(half %a1, half %a2) #0 {
+entry:
+  ;CHECK: sqrshl {{h[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
+  %0 = tail call half asm "sqrshl ${0:h}, ${1:h}, ${2:h}", "=w,w,w"(half %a1, half %a1) #1
+  ret half %0
+}
Index: lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- lib/Target/AArch64/AArch64ISelLowering.cpp
+++ lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -4700,6 +4700,8 @@
         return std::make_pair(0U, &AArch64::GPR64commonRegClass);
       return std::make_pair(0U, &AArch64::GPR32commonRegClass);
     case 'w':
+      if (VT.getSizeInBits() == 16)
+        return std::make_pair(0U, &AArch64::FPR16RegClass);
       if (VT.getSizeInBits() == 32)
         return std::make_pair(0U, &AArch64::FPR32RegClass);
       if (VT.getSizeInBits() == 64)


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