[llvm] r282626 - IfConversion: Add implicit uses for redefined regs with live subregisters

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Wed Sep 28 15:07:41 2016
New Revision: 282626

URL: http://llvm.org/viewvc/llvm-project?rev=282626&view=rev
Log:
IfConversion: Add implicit uses for redefined regs with live subregisters

Normally, if conversion would add implicit uses for redefined registers,
e.g. R0<def> = add_if ..., R0<imp-use>. However, if only subregisters of
R0 are known to be live but not R0 itself, such implicit uses will not be
added, causing prior definitions of such subregisters and R0 itself to
become dead.

Added:
    llvm/trunk/test/CodeGen/Hexagon/ifcvt-live-subreg.mir
Modified:
    llvm/trunk/lib/CodeGen/IfConversion.cpp

Modified: llvm/trunk/lib/CodeGen/IfConversion.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/IfConversion.cpp?rev=282626&r1=282625&r2=282626&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/IfConversion.cpp (original)
+++ llvm/trunk/lib/CodeGen/IfConversion.cpp Wed Sep 28 15:07:41 2016
@@ -1453,6 +1453,17 @@ static void UpdatePredRedefs(MachineInst
     }
     if (LiveBeforeMI.count(Reg))
       MIB.addReg(Reg, RegState::Implicit);
+    else {
+      bool HasLiveSubReg = false;
+      for (MCSubRegIterator S(Reg, TRI); S.isValid(); ++S) {
+        if (!LiveBeforeMI.count(*S))
+          continue;
+        HasLiveSubReg = true;
+        break;
+      }
+      if (HasLiveSubReg)
+        MIB.addReg(Reg, RegState::Implicit);
+    }
   }
 }
 

Added: llvm/trunk/test/CodeGen/Hexagon/ifcvt-live-subreg.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/ifcvt-live-subreg.mir?rev=282626&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/ifcvt-live-subreg.mir (added)
+++ llvm/trunk/test/CodeGen/Hexagon/ifcvt-live-subreg.mir Wed Sep 28 15:07:41 2016
@@ -0,0 +1,50 @@
+# RUN: llc -march=hexagon -run-pass if-converter -o - %s | FileCheck %s
+# Check that an implicit use is generated for a predicated instruction
+# when a subregister of the redefined register is live.
+
+# CHECK-LABEL: name: foo
+
+# Verify the predicated block:
+# CHECK-LABEL: bb.0:
+# CHECK: liveins: %r0, %r1, %p0, %d8
+# CHECK: %d8 = A2_combinew killed %r0, killed %r1
+# CHECK: %d8 = L2_ploadrdf_io %p0, %r29, 0, implicit %d8
+# CHECK: J2_jumprf %p0, killed %r31, implicit-def %pc, implicit-def %pc, implicit killed %d8
+
+--- |
+  define void @foo() {
+    ret void
+  }
+...
+
+
+---
+name:            foo
+alignment:       4
+tracksRegLiveness: true
+liveins:
+  - { reg: '%r0' }
+  - { reg: '%r1' }
+  - { reg: '%p0' }
+  - { reg: '%d8' }
+body:             |
+  bb.0:
+    successors: %bb.1, %bb.2
+    liveins: %r0, %r1, %p0, %d8
+    %d8 = A2_combinew killed %r0, killed %r1
+    J2_jumpf killed %p0, %bb.2, implicit-def %pc
+
+  bb.1:
+    liveins: %d0, %r17
+    %r0 = A2_tfrsi 0
+    %r1 = A2_tfrsi 0
+    A2_nop ; non-predicable
+    J2_jumpr killed %r31, implicit-def dead %pc, implicit killed %d0
+
+  bb.2:
+    ; Predicate this block.
+    %d8 = L2_loadrd_io %r29, 0
+    J2_jumpr killed %r31, implicit-def dead %pc, implicit killed %d8
+
+...
+