[PATCH] D21571: [AArch64] Avoid generating indexed vector instructions for Exynos

[Sebastian Pop via llvm-commits]

sebpop added inline comments.

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Comment at: llvm/lib/Target/AArch64/AArch64VectorByElementOpt.cpp:12
@@ +11,3 @@
+// SIMD instructions.
+//
+//===----------------------------------------------------------------------===//
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Let's add a bit more description of what this pass does, and an example from below...

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Comment at: llvm/lib/Target/AArch64/AArch64VectorByElementOpt.cpp:131
@@ +130,3 @@
+    return true;
+  } else {
+    VecInstElemTable[InstDesc->getOpcode()] = false;
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Remove the else as there is a return stmt in then clause.

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Comment at: llvm/lib/Target/AArch64/AArch64VectorByElementOpt.cpp:167
@@ +166,3 @@
+///
+/// Example:
+///    fmla v0.4s, v1.4s, v2.s[1]
----------------
... this example, and the comment at the top of the file can contain some of the text above.

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Comment at: llvm/lib/Target/AArch64/AArch64VectorByElementOpt.cpp:177
@@ +176,3 @@
+  const TargetRegisterClass *RC = &AArch64::FPR128RegClass;
+  ;
+
----------------
Remove this empty stmt.

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Comment at: llvm/test/CodeGen/AArch64/arm64-neon-2velem.ll:2
@@ -1,2 +1,3 @@
 ; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon -fp-contract=fast | FileCheck %s
+; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon -fp-contract=fast -mcpu=exynos-m1 | FileCheck --check-prefix=EXYNOS %s
 
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Let's also add a comment here saying that we need the instructions cost of Exynos-M1 to trigger the transform.


https://reviews.llvm.org/D21571