[llvm] r282588 - [AVR] Merge most recent changes to AVRInstrInfo.td
Dylan McKay via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 28 06:44:02 PDT 2016
Author: dylanmckay
Date: Wed Sep 28 08:44:02 2016
New Revision: 282588
URL: http://llvm.org/viewvc/llvm-project?rev=282588&view=rev
Log:
[AVR] Merge most recent changes to AVRInstrInfo.td
This adds two new things:
- Operand types per fixup
- Atomic pseudo operations
Modified:
llvm/trunk/lib/Target/AVR/AVRInstrInfo.td
Modified: llvm/trunk/lib/Target/AVR/AVRInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AVR/AVRInstrInfo.td?rev=282588&r1=282587&r2=282588&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AVR/AVRInstrInfo.td (original)
+++ llvm/trunk/lib/Target/AVR/AVRInstrInfo.td Wed Sep 28 08:44:02 2016
@@ -155,7 +155,7 @@ def memspi : Operand<iPTR>
let MIOperandInfo = (ops GPRSP, i16imm);
}
-def i8imm_com : Operand<i8>
+def imm_com8 : Operand<i8>
{
let EncoderMethod = "encodeComplement";
@@ -180,6 +180,38 @@ def call_target : Operand<iPTR>
let EncoderMethod = "encodeCallTarget";
}
+// A 16-bit address (which can lead to an R_AVR_16 relocation).
+def imm16 : Operand<i16>
+{
+ let EncoderMethod = "encodeImm<AVR::fixup_16>";
+}
+
+/// A 6-bit immediate used in the ADIW/SBIW instructions.
+def imm_arith6 : Operand<i16>
+{
+ let EncoderMethod = "encodeImm<AVR::fixup_6_adiw>";
+}
+
+/// An 8-bit immediate inside an instruction with the same format
+/// as the `LDI` instruction (the `FRdK` format).
+def imm_ldi8 : Operand<i8>
+{
+ let EncoderMethod = "encodeImm<AVR::fixup_ldi>";
+}
+
+/// A 5-bit port number used in SBIC and friends (the `FIOBIT` format).
+def imm_port5 : Operand<i8>
+{
+ let EncoderMethod = "encodeImm<AVR::fixup_port5>";
+}
+
+/// A 6-bit port number used in the `IN` instruction and friends (the
+/// `FIORdA` format.
+def imm_port6 : Operand<i8>
+{
+ let EncoderMethod = "encodeImm<AVR::fixup_port6>";
+}
+
// Addressing mode pattern reg+imm6
def addr : ComplexPattern<iPTR, 2, "SelectAddr", [], [SDNPWantRoot]>;
@@ -372,7 +404,7 @@ Defs = [SREG] in
// Adds an immediate 6-bit value K to Rd, placing the result in Rd.
def ADIWRdK : FWRdK<0b0,
(outs IWREGS:$rd),
- (ins IWREGS:$src, i16imm:$k),
+ (ins IWREGS:$src, imm_arith6:$k),
"adiw\t$rd, $k",
[(set i16:$rd, (add i16:$src, uimm6:$k)),
(implicit SREG)]>,
@@ -409,7 +441,7 @@ Defs = [SREG] in
def SUBIRdK : FRdK<0b0101,
(outs LD8:$rd),
- (ins LD8:$src, i8imm:$k),
+ (ins LD8:$src, imm_ldi8:$k),
"subi\t$rd, $k",
[(set i8:$rd, (sub i8:$src, imm:$k)),
(implicit SREG)]>;
@@ -427,7 +459,7 @@ Defs = [SREG] in
def SBIWRdK : FWRdK<0b1,
(outs IWREGS:$rd),
- (ins IWREGS:$src, i16imm:$k),
+ (ins IWREGS:$src, imm_arith6:$k),
"sbiw\t$rd, $k",
[(set i16:$rd, (sub i16:$src, uimm6:$k)),
(implicit SREG)]>,
@@ -457,7 +489,7 @@ Defs = [SREG] in
def SBCIRdK : FRdK<0b0100,
(outs LD8:$rd),
- (ins LD8:$src, i8imm:$k),
+ (ins LD8:$src, imm_ldi8:$k),
"sbci\t$rd, $k",
[(set i8:$rd, (sube i8:$src, imm:$k)),
(implicit SREG)]>;
@@ -626,7 +658,7 @@ Defs = [SREG] in
def ANDIRdK : FRdK<0b0111,
(outs LD8:$rd),
- (ins LD8:$src, i8imm:$k),
+ (ins LD8:$src, imm_ldi8:$k),
"andi\t$rd, $k",
[(set i8:$rd, (and i8:$src, imm:$k)),
(implicit SREG)]>;
@@ -644,7 +676,7 @@ Defs = [SREG] in
def ORIRdK : FRdK<0b0110,
(outs LD8:$rd),
- (ins LD8:$src, i8imm:$k),
+ (ins LD8:$src, imm_ldi8:$k),
"ori\t$rd, $k",
[(set i8:$rd, (or i8:$src, imm:$k)),
(implicit SREG)]>;
@@ -871,7 +903,7 @@ let Defs = [SREG] in
let Uses = [SREG] in
def CPIRdK : FRdK<0b0011,
(outs),
- (ins GPR8:$rd, i8imm:$k),
+ (ins GPR8:$rd, imm_ldi8:$k),
"cpi\t$rd, $k",
[(AVRcmp i8:$rd, imm:$k), (implicit SREG)]>;
}
@@ -900,13 +932,13 @@ isTerminator = 1 in
def SBICAb : FIOBIT<0b01,
(outs),
- (ins i16imm:$a, i8imm:$b),
+ (ins imm_port5:$a, i8imm:$b),
"sbic\t$a, $b",
[]>;
def SBISAb : FIOBIT<0b11,
(outs),
- (ins i16imm:$a, i8imm:$b),
+ (ins imm_port5:$a, i8imm:$b),
"sbis\t$a, $b",
[]>;
}
@@ -1065,7 +1097,7 @@ let isReMaterializable = 1 in
{
def LDIRdK : FRdK<0b1110,
(outs LD8:$rd),
- (ins i8imm:$k),
+ (ins imm_ldi8:$k),
"ldi\t$rd, $k",
[(set i8:$rd, imm:$k)]>;
@@ -1086,7 +1118,7 @@ isReMaterializable = 1 in
{
def LDSRdK : F32DM<0b0,
(outs GPR8:$rd),
- (ins i16imm:$k),
+ (ins imm16:$k),
"lds\t$rd, $k",
[(set i8:$rd, (load imm:$k))]>,
Requires<[HasSRAM]>;
@@ -1194,8 +1226,6 @@ isReMaterializable = 1 in
[(set i16:$dst, (load addr:$memri))]>,
Requires<[HasSRAM]>;
- //:FIXME: remove this once PR13375 gets fixed
- // Bug report: https://llvm.org/bugs/show_bug.cgi?id=13375
let mayLoad = 1,
hasSideEffects = 0 in
def LDDWRdYQ : Pseudo<(outs DREGS:$dst),
@@ -1205,10 +1235,42 @@ isReMaterializable = 1 in
Requires<[HasSRAM]>;
}
+class AtomicLoad<PatFrag Op, RegisterClass DRC> :
+ Pseudo<(outs DRC:$rd), (ins PTRREGS:$rr), "atomic_op",
+ [(set DRC:$rd, (Op i16:$rr))]>;
+
+class AtomicStore<PatFrag Op, RegisterClass DRC> :
+ Pseudo<(outs), (ins PTRDISPREGS:$rd, DRC:$rr), "atomic_op",
+ [(Op i16:$rd, DRC:$rr)]>;
+
+class AtomicLoadOp<PatFrag Op, RegisterClass DRC> :
+ Pseudo<(outs DRC:$rd), (ins PTRREGS:$rr, DRC:$operand),
+ "atomic_op",
+ [(set DRC:$rd, (Op i16:$rr, DRC:$operand))]>;
+
+def AtomicLoad8 : AtomicLoad<atomic_load_8, GPR8>;
+def AtomicLoad16 : AtomicLoad<atomic_load_16, DREGS>;
+
+def AtomicStore8 : AtomicStore<atomic_store_8, GPR8>;
+def AtomicStore16 : AtomicStore<atomic_store_16, DREGS>;
+
+def AtomicLoadAdd8 : AtomicLoadOp<atomic_load_add_8, GPR8>;
+def AtomicLoadAdd16 : AtomicLoadOp<atomic_load_add_16, DREGS>;
+def AtomicLoadSub8 : AtomicLoadOp<atomic_load_sub_8, GPR8>;
+def AtomicLoadSub16 : AtomicLoadOp<atomic_load_sub_16, DREGS>;
+def AtomicLoadAnd8 : AtomicLoadOp<atomic_load_and_8, GPR8>;
+def AtomicLoadAnd16 : AtomicLoadOp<atomic_load_and_16, DREGS>;
+def AtomicLoadOr8 : AtomicLoadOp<atomic_load_or_8, GPR8>;
+def AtomicLoadOr16 : AtomicLoadOp<atomic_load_or_16, DREGS>;
+def AtomicLoadXor8 : AtomicLoadOp<atomic_load_xor_8, GPR8>;
+def AtomicLoadXor16 : AtomicLoadOp<atomic_load_xor_16, DREGS>;
+def AtomicFence : Pseudo<(outs), (ins), "atomic_fence",
+ [(atomic_fence imm, imm)]>;
+
// Indirect store from register to data space.
def STSKRr : F32DM<0b1,
(outs),
- (ins i16imm:$k, GPR8:$rd),
+ (ins imm16:$k, GPR8:$rd),
"sts\t$k, $rd",
[(store i8:$rd, imm:$k)]>,
Requires<[HasSRAM]>;
@@ -1433,7 +1495,7 @@ let canFoldAsLoad = 1,
isReMaterializable = 1 in
{
def INRdA : FIORdA<(outs GPR8:$dst),
- (ins i16imm:$src),
+ (ins imm_port6:$src),
"in\t$dst, $src",
[(set i8:$dst, (load ioaddr8:$src))]>;
@@ -1445,7 +1507,7 @@ isReMaterializable = 1 in
// Write data to IO location operations.
def OUTARr : FIOARr<(outs),
- (ins i16imm:$dst, GPR8:$src),
+ (ins imm_port6:$dst, GPR8:$src),
"out\t$dst, $src",
[(store i8:$src, ioaddr8:$dst)]>;
@@ -1613,14 +1675,14 @@ def SWAPRd : FRd<0b1001,
// instead of in+ori+out which requires one more instr.
def SBIAb : FIOBIT<0b10,
(outs),
- (ins i16imm:$addr, i8imm:$bit),
+ (ins imm_port5:$addr, i8imm:$bit),
"sbi\t$addr, $bit",
[(store (or (i8 (load lowioaddr8:$addr)), iobitpos8:$bit),
lowioaddr8:$addr)]>;
def CBIAb : FIOBIT<0b00,
(outs),
- (ins i16imm:$addr, i8imm:$bit),
+ (ins imm_port5:$addr, i8imm:$bit),
"cbi\t$addr, $bit",
[(store (and (i8 (load lowioaddr8:$addr)), iobitposn8:$bit),
lowioaddr8:$addr)]>;
@@ -1648,16 +1710,18 @@ Defs = [SREG] in
// Alias for ORI Rd, K
def SBRRdK : FRdK<0b0110,
(outs LD8:$rd),
- (ins LD8:$src, i8imm:$k),
+ (ins LD8:$src, imm_ldi8:$k),
"sbr\t$rd, $k",
[(set i8:$rd, (or i8:$src, imm:$k)),
(implicit SREG)]>;
// CBR Rd, K
// Alias for `ANDI Rd, COM(K)` where COM(K) is the compliment of K.
+ // FIXME: This uses the 'complement' encoder. We need it to also use the
+ // imm_ldi8 encoder. This will cause no fixups to be created on this instruction.
def CBRRdK : FRdK<0b0111,
(outs LD8:$rd),
- (ins LD8:$src, i8imm_com:$k),
+ (ins LD8:$src, imm_com8:$k),
"cbr\t$rd, $k",
[]>;
}
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