[llvm] r282550 - [AArch64][RegisterBankInfo] Switch to statically allocated ValueMapping.

[Quentin Colombet via llvm-commits]

Author: qcolombet
Date: Tue Sep 27 17:55:04 2016
New Revision: 282550

URL: http://llvm.org/viewvc/llvm-project?rev=282550&view=rev
Log:
[AArch64][RegisterBankInfo] Switch to statically allocated ValueMapping.

Another step toward TableGen'ed like structure for the RegisterBankInfo
of AArch64. By doing this, we also save a bit of compile time for the
exact same output.

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64GenRegisterBankInfo.def
    llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp

Modified: llvm/trunk/lib/Target/AArch64/AArch64GenRegisterBankInfo.def
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64GenRegisterBankInfo.def?rev=282550&r1=282549&r2=282550&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64GenRegisterBankInfo.def (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64GenRegisterBankInfo.def Tue Sep 27 17:55:04 2016
@@ -65,5 +65,24 @@ RegisterBankInfo::PartialMapping PartMap
   {0, 512, FPRRegBank}
 };
 
+// ValueMappings.
+RegisterBankInfo::ValueMapping ValMappings[] {
+  /* BreakDown, NumBreakDowns */
+  // 0: GPR 32-bit value.
+  {&PartMappings[0], 1},
+  // 1: GPR 64-bit value.
+  {&PartMappings[1], 1},
+  // 2: FPR 32-bit value.
+  {&PartMappings[2], 1},
+  // 3: FPR 64-bit value.
+  {&PartMappings[3], 1},
+  // 4: FPR 128-bit value.
+  {&PartMappings[4], 1},
+  // 5: FPR 256-bit value.
+  {&PartMappings[5], 1},
+  // 6: FPR 512-bit value.
+  {&PartMappings[6], 1}
+};
+
 } // End AArch64 namespace.
 } // End llvm namespace.

Modified: llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp?rev=282550&r1=282549&r2=282550&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp Tue Sep 27 17:55:04 2016
@@ -205,15 +205,11 @@ AArch64RegisterBankInfo::getInstrAlterna
     InstructionMapping FPRMapping(/*ID*/ 2, /*Cost*/ 1, /*NumOperands*/ 3);
     for (unsigned Idx = 0; Idx != 3; ++Idx) {
       GPRMapping.setOperandMapping(
-          Idx, getValueMapping(
-                   &AArch64::PartMappings[AArch64::getRegBankBaseIdx(Size) +
-                                          AArch64::FirstGPR],
-                   1));
+          Idx, AArch64::ValMappings[AArch64::getRegBankBaseIdx(Size) +
+                                    AArch64::FirstGPR]);
       FPRMapping.setOperandMapping(
-          Idx, getValueMapping(
-                   &AArch64::PartMappings[AArch64::getRegBankBaseIdx(Size) +
-                                          AArch64::FirstFPR],
-                   1));
+          Idx, AArch64::ValMappings[AArch64::getRegBankBaseIdx(Size) +
+                                    AArch64::FirstFPR]);
     }
     AltMappings.emplace_back(std::move(GPRMapping));
     AltMappings.emplace_back(std::move(FPRMapping));
@@ -324,8 +320,7 @@ AArch64RegisterBankInfo::getInstrMapping
   // Finally construct the computed mapping.
   for (unsigned Idx = 0; Idx < MI.getNumOperands(); ++Idx)
     if (MI.getOperand(Idx).isReg())
-      Mapping.setOperandMapping(
-          Idx, getValueMapping(&AArch64::PartMappings[OpFinalIdx[Idx]], 1));
+      Mapping.setOperandMapping(Idx, AArch64::ValMappings[OpFinalIdx[Idx]]);
 
   return Mapping;
 }