[PATCH] D24924: [PPC] Better codegen for AND, ANY_EXT, SRL sequence

[Hal Finkel via llvm-commits]

hfinkel added inline comments.

================
Comment at: lib/Target/PowerPC/PPCISelDAGToDAG.cpp:2647
@@ +2646,3 @@
+
+        Val = SDValue(CurDAG->getMachineNode(PPC::INSERT_SUBREG, dl, ResultType,
+                      IDVal, Op0.getOperand(0), getI32Imm(1, dl)), 0);
----------------
amehsan wrote:
> hfinkel wrote:
> > We shouldn't speculatively create new nodes if we can avoid it.
> Sorry, I am not sure I understand this comment. What is speculative here? I have a i32 and want to convert it to i64.  I tried a couple of different options and this sequence was the only one that worked. This appeared in a small kernel that I wrote and included a similar conversion.
> 
> 
No, I mean that you're calling getMachineNode here to generate new SDAG nodes; are you sure that when you do this one of the conditions below will match and these will never just end up being garbage collected?


https://reviews.llvm.org/D24924