[llvm] r282396 - Revert "[AMDGPU] Disassembler: print label names in branch instructions"
Sam Kolton via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 26 04:29:04 PDT 2016
Author: skolton
Date: Mon Sep 26 06:29:03 2016
New Revision: 282396
URL: http://llvm.org/viewvc/llvm-project?rev=282396&view=rev
Log:
Revert "[AMDGPU] Disassembler: print label names in branch instructions"
This reverts commit 6c6dbe625263ec9fcf8de0df27263cf147cde550.
Modified:
llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td
llvm/trunk/test/MC/AMDGPU/labels-branch.s
llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp
Modified: llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp?rev=282396&r1=282395&r2=282396&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp Mon Sep 26 06:29:03 2016
@@ -28,7 +28,6 @@
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCSubtargetInfo.h"
-#include "llvm/Support/ELF.h"
#include "llvm/Support/Endian.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/TargetRegistry.h"
@@ -49,18 +48,6 @@ addOperand(MCInst &Inst, const MCOperand
MCDisassembler::SoftFail;
}
-static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm,
- uint64_t Addr, const void *Decoder) {
- auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
-
- APInt SignedOffset(18, Imm * 4, true);
- int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue();
-
- if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2))
- return MCDisassembler::Success;
- return addOperand(Inst, MCOperand::createImm(Imm));
-}
-
#define DECODE_OPERAND2(RegClass, DecName) \
static DecodeStatus Decode##RegClass##RegisterClass(MCInst &Inst, \
unsigned Imm, \
@@ -444,50 +431,6 @@ MCOperand AMDGPUDisassembler::decodeSpec
return errOperand(Val, "unknown operand encoding " + Twine(Val));
}
-//===----------------------------------------------------------------------===//
-// AMDGPUSymbolizer
-//===----------------------------------------------------------------------===//
-
-// Try to find symbol name for specified label
-bool AMDGPUSymbolizer::tryAddingSymbolicOperand(MCInst &Inst,
- raw_ostream &/*cStream*/, int64_t Value,
- uint64_t /*Address*/, bool IsBranch,
- uint64_t /*Offset*/, uint64_t /*InstSize*/) {
- typedef std::tuple<uint64_t, StringRef, uint8_t> SymbolInfoTy;
- typedef std::vector<SymbolInfoTy> SectionSymbolsTy;
-
- if (!IsBranch) {
- return false;
- }
-
- auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo);
- auto Result = std::find_if(Symbols->begin(), Symbols->end(),
- [Value](const SymbolInfoTy& Val) {
- return std::get<0>(Val) == static_cast<uint64_t>(Value)
- && std::get<2>(Val) == ELF::STT_NOTYPE;
- });
- if (Result != Symbols->end()) {
- auto *Sym = Ctx.getOrCreateSymbol(std::get<1>(*Result));
- const auto *Add = MCSymbolRefExpr::create(Sym, Ctx);
- Inst.addOperand(MCOperand::createExpr(Add));
- return true;
- }
- return false;
-}
-
-//===----------------------------------------------------------------------===//
-// Initialization
-//===----------------------------------------------------------------------===//
-
-static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/,
- LLVMOpInfoCallback /*GetOpInfo*/,
- LLVMSymbolLookupCallback /*SymbolLookUp*/,
- void *DisInfo,
- MCContext *Ctx,
- std::unique_ptr<MCRelocationInfo> &&RelInfo) {
- return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo);
-}
-
static MCDisassembler *createAMDGPUDisassembler(const Target &T,
const MCSubtargetInfo &STI,
MCContext &Ctx) {
@@ -496,5 +439,4 @@ static MCDisassembler *createAMDGPUDisas
extern "C" void LLVMInitializeAMDGPUDisassembler() {
TargetRegistry::RegisterMCDisassembler(TheGCNTarget, createAMDGPUDisassembler);
- TargetRegistry::RegisterMCSymbolizer(TheGCNTarget, createAMDGPUSymbolizer);
}
Modified: llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h?rev=282396&r1=282395&r2=282396&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h (original)
+++ llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h Mon Sep 26 06:29:03 2016
@@ -18,107 +18,76 @@
#include "llvm/ADT/ArrayRef.h"
#include "llvm/MC/MCDisassembler/MCDisassembler.h"
-#include "llvm/MC/MCDisassembler/MCSymbolizer.h"
namespace llvm {
-class MCContext;
-class MCInst;
-class MCOperand;
-class MCSubtargetInfo;
-class Twine;
-
-//===----------------------------------------------------------------------===//
-// AMDGPUDisassembler
-//===----------------------------------------------------------------------===//
-
-class AMDGPUDisassembler : public MCDisassembler {
-private:
- mutable ArrayRef<uint8_t> Bytes;
-
-public:
- AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
- MCDisassembler(STI, Ctx) {}
-
- ~AMDGPUDisassembler() {}
-
- DecodeStatus getInstruction(MCInst &MI, uint64_t &Size,
- ArrayRef<uint8_t> Bytes, uint64_t Address,
- raw_ostream &WS, raw_ostream &CS) const override;
-
- const char* getRegClassName(unsigned RegClassID) const;
-
- MCOperand createRegOperand(unsigned int RegId) const;
- MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
- MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const;
-
- MCOperand errOperand(unsigned V, const llvm::Twine& ErrMsg) const;
-
- DecodeStatus tryDecodeInst(const uint8_t* Table,
- MCInst &MI,
- uint64_t Inst,
- uint64_t Address) const;
-
- MCOperand decodeOperand_VGPR_32(unsigned Val) const;
- MCOperand decodeOperand_VS_32(unsigned Val) const;
- MCOperand decodeOperand_VS_64(unsigned Val) const;
-
- MCOperand decodeOperand_VReg_64(unsigned Val) const;
- MCOperand decodeOperand_VReg_96(unsigned Val) const;
- MCOperand decodeOperand_VReg_128(unsigned Val) const;
-
- MCOperand decodeOperand_SReg_32(unsigned Val) const;
- MCOperand decodeOperand_SReg_32_XM0(unsigned Val) const;
- MCOperand decodeOperand_SReg_64(unsigned Val) const;
- MCOperand decodeOperand_SReg_128(unsigned Val) const;
- MCOperand decodeOperand_SReg_256(unsigned Val) const;
- MCOperand decodeOperand_SReg_512(unsigned Val) const;
-
- enum OpWidthTy {
- OPW32,
- OPW64,
- OPW128,
- OPW_LAST_,
- OPW_FIRST_ = OPW32
+ class MCContext;
+ class MCInst;
+ class MCOperand;
+ class MCSubtargetInfo;
+ class Twine;
+
+ class AMDGPUDisassembler : public MCDisassembler {
+ private:
+ mutable ArrayRef<uint8_t> Bytes;
+
+ public:
+ AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
+ MCDisassembler(STI, Ctx) {}
+
+ ~AMDGPUDisassembler() {}
+
+ DecodeStatus getInstruction(MCInst &MI, uint64_t &Size,
+ ArrayRef<uint8_t> Bytes, uint64_t Address,
+ raw_ostream &WS, raw_ostream &CS) const override;
+
+ const char* getRegClassName(unsigned RegClassID) const;
+
+ MCOperand createRegOperand(unsigned int RegId) const;
+ MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
+ MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const;
+
+ MCOperand errOperand(unsigned V, const llvm::Twine& ErrMsg) const;
+
+ DecodeStatus tryDecodeInst(const uint8_t* Table,
+ MCInst &MI,
+ uint64_t Inst,
+ uint64_t Address) const;
+
+ MCOperand decodeOperand_VGPR_32(unsigned Val) const;
+ MCOperand decodeOperand_VS_32(unsigned Val) const;
+ MCOperand decodeOperand_VS_64(unsigned Val) const;
+
+ MCOperand decodeOperand_VReg_64(unsigned Val) const;
+ MCOperand decodeOperand_VReg_96(unsigned Val) const;
+ MCOperand decodeOperand_VReg_128(unsigned Val) const;
+
+ MCOperand decodeOperand_SReg_32(unsigned Val) const;
+ MCOperand decodeOperand_SReg_32_XM0(unsigned Val) const;
+ MCOperand decodeOperand_SReg_64(unsigned Val) const;
+ MCOperand decodeOperand_SReg_128(unsigned Val) const;
+ MCOperand decodeOperand_SReg_256(unsigned Val) const;
+ MCOperand decodeOperand_SReg_512(unsigned Val) const;
+
+ enum OpWidthTy {
+ OPW32,
+ OPW64,
+ OPW128,
+ OPW_LAST_,
+ OPW_FIRST_ = OPW32
+ };
+ unsigned getVgprClassId(const OpWidthTy Width) const;
+ unsigned getSgprClassId(const OpWidthTy Width) const;
+ unsigned getTtmpClassId(const OpWidthTy Width) const;
+
+ static MCOperand decodeIntImmed(unsigned Imm);
+ static MCOperand decodeFPImmed(bool Is32, unsigned Imm);
+ MCOperand decodeLiteralConstant() const;
+
+ MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val) const;
+ MCOperand decodeSpecialReg32(unsigned Val) const;
+ MCOperand decodeSpecialReg64(unsigned Val) const;
};
- unsigned getVgprClassId(const OpWidthTy Width) const;
- unsigned getSgprClassId(const OpWidthTy Width) const;
- unsigned getTtmpClassId(const OpWidthTy Width) const;
-
- static MCOperand decodeIntImmed(unsigned Imm);
- static MCOperand decodeFPImmed(bool Is32, unsigned Imm);
- MCOperand decodeLiteralConstant() const;
-
- MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val) const;
- MCOperand decodeSpecialReg32(unsigned Val) const;
- MCOperand decodeSpecialReg64(unsigned Val) const;
-};
-
-//===----------------------------------------------------------------------===//
-// AMDGPUSymbolizer
-//===----------------------------------------------------------------------===//
-
-class AMDGPUSymbolizer : public MCSymbolizer {
-private:
- void *DisInfo;
-
-public:
- AMDGPUSymbolizer(MCContext &Ctx, std::unique_ptr<MCRelocationInfo> &&RelInfo,
- void *disInfo)
- : MCSymbolizer(Ctx, std::move(RelInfo)), DisInfo(disInfo) {}
-
- bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream,
- int64_t Value, uint64_t Address,
- bool IsBranch, uint64_t Offset,
- uint64_t InstSize) override;
-
- void tryAddingPcLoadReferenceComment(raw_ostream &cStream,
- int64_t Value,
- uint64_t Address) override {
- assert(false && "Implement if needed");
- }
-};
-
} // namespace llvm
#endif //LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td?rev=282396&r1=282395&r2=282396&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td Mon Sep 26 06:29:03 2016
@@ -291,7 +291,6 @@ def SoppBrTarget : AsmOperandClass {
def sopp_brtarget : Operand<OtherVT> {
let EncoderMethod = "getSOPPBrEncoding";
- let DecoderMethod = "decodeSoppBrTarget";
let OperandType = "OPERAND_PCREL";
let ParserMatchClass = SoppBrTarget;
}
Modified: llvm/trunk/test/MC/AMDGPU/labels-branch.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/labels-branch.s?rev=282396&r1=282395&r2=282396&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/labels-branch.s (original)
+++ llvm/trunk/test/MC/AMDGPU/labels-branch.s Mon Sep 26 06:29:03 2016
@@ -6,19 +6,19 @@ s_branch loop_start
// VI: s_branch loop_start ; encoding: [A,A,0x82,0xbf]
// VI-NEXT: ; fixup A - offset: 0, value: loop_start, kind: fixup_si_sopp_br
// BIN: loop_start:
-// BIN-NEXT: s_branch loop_start // 000000000000: BF82FFFF
+// BIN-NEXT: BF82FFFF
s_branch loop_end
// VI: s_branch loop_end ; encoding: [A,A,0x82,0xbf]
// VI-NEXT: ; fixup A - offset: 0, value: loop_end, kind: fixup_si_sopp_br
-// BIN: s_branch loop_end // 000000000004: BF820000
+// BIN: BF820000
// BIN: loop_end:
loop_end:
s_branch gds
// VI: s_branch gds ; encoding: [A,A,0x82,0xbf]
// VI-NEXT: ; fixup A - offset: 0, value: gds, kind: fixup_si_sopp_br
-// BIN: s_branch gds // 000000000008: BF820000
+// BIN: BF820000
// BIN: gds:
gds:
s_nop 0
Modified: llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp?rev=282396&r1=282395&r2=282396&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp (original)
+++ llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp Mon Sep 26 06:29:03 2016
@@ -1228,18 +1228,6 @@ static void DisassembleObject(const Obje
std::sort(DataMappingSymsAddr.begin(), DataMappingSymsAddr.end());
std::sort(TextMappingSymsAddr.begin(), TextMappingSymsAddr.end());
- if (Obj->isELF() && Obj->getArch() == Triple::amdgcn) {
- // AMDGPU disassembler uses symbolizer for printing labels
- std::unique_ptr<MCRelocationInfo> RelInfo(
- TheTarget->createMCRelocationInfo(TripleName, Ctx));
- if (RelInfo) {
- std::unique_ptr<MCSymbolizer> Symbolizer(
- TheTarget->createMCSymbolizer(
- TripleName, nullptr, nullptr, &Symbols, &Ctx, std::move(RelInfo)));
- DisAsm->setSymbolizer(std::move(Symbolizer));
- }
- }
-
// Make a list of all the relocations for this section.
std::vector<RelocationRef> Rels;
if (InlineRelocs) {
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