[llvm] r282356 - [AVX-512] Add the scalar unsigned integer to fp conversion instructions to hasUndefRegUpdate.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sun Sep 25 09:33:57 PDT 2016
Author: ctopper
Date: Sun Sep 25 11:33:57 2016
New Revision: 282356
URL: http://llvm.org/viewvc/llvm-project?rev=282356&view=rev
Log:
[AVX-512] Add the scalar unsigned integer to fp conversion instructions to hasUndefRegUpdate.
Modified:
llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
llvm/trunk/test/CodeGen/X86/avx512-cvt.ll
llvm/trunk/test/CodeGen/X86/vec_int_to_fp.ll
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=282356&r1=282355&r2=282356&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Sun Sep 25 11:33:57 2016
@@ -6397,6 +6397,22 @@ static bool hasUndefRegUpdate(unsigned O
case X86::VCVTSI642SDZrm:
case X86::VCVTSI642SDZrr_Int:
case X86::VCVTSI642SDZrm_Int:
+ case X86::VCVTUSI2SSZrr:
+ case X86::VCVTUSI2SSZrm:
+ case X86::VCVTUSI2SSZrr_Int:
+ case X86::VCVTUSI2SSZrm_Int:
+ case X86::VCVTUSI642SSZrr:
+ case X86::VCVTUSI642SSZrm:
+ case X86::VCVTUSI642SSZrr_Int:
+ case X86::VCVTUSI642SSZrm_Int:
+ case X86::VCVTUSI2SDZrr:
+ case X86::VCVTUSI2SDZrm:
+ case X86::VCVTUSI2SDZrr_Int:
+ case X86::VCVTUSI2SDZrm_Int:
+ case X86::VCVTUSI642SDZrr:
+ case X86::VCVTUSI642SDZrm:
+ case X86::VCVTUSI642SDZrr_Int:
+ case X86::VCVTUSI642SDZrm_Int:
case X86::VCVTSD2SSZrr:
case X86::VCVTSD2SSZrm:
case X86::VCVTSS2SDZrr:
Modified: llvm/trunk/test/CodeGen/X86/avx512-cvt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-cvt.ll?rev=282356&r1=282355&r2=282356&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-cvt.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-cvt.ll Sun Sep 25 11:33:57 2016
@@ -207,16 +207,16 @@ define <4 x float> @ultof432(<4 x i64> %
; KNL-LABEL: ultof432:
; KNL: ## BB#0:
; KNL-NEXT: vpextrq $1, %xmm0, %rax
-; KNL-NEXT: vcvtusi2ssq %rax, %xmm0, %xmm1
+; KNL-NEXT: vcvtusi2ssq %rax, %xmm1, %xmm1
; KNL-NEXT: vmovq %xmm0, %rax
-; KNL-NEXT: vcvtusi2ssq %rax, %xmm0, %xmm2
+; KNL-NEXT: vcvtusi2ssq %rax, %xmm2, %xmm2
; KNL-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3]
; KNL-NEXT: vextracti128 $1, %ymm0, %xmm0
; KNL-NEXT: vmovq %xmm0, %rax
-; KNL-NEXT: vcvtusi2ssq %rax, %xmm0, %xmm2
+; KNL-NEXT: vcvtusi2ssq %rax, %xmm3, %xmm2
; KNL-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3]
; KNL-NEXT: vpextrq $1, %xmm0, %rax
-; KNL-NEXT: vcvtusi2ssq %rax, %xmm0, %xmm0
+; KNL-NEXT: vcvtusi2ssq %rax, %xmm3, %xmm0
; KNL-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; KNL-NEXT: retq
;
@@ -233,27 +233,27 @@ define <8 x double> @ultof64(<8 x i64> %
; KNL: ## BB#0:
; KNL-NEXT: vextracti32x4 $3, %zmm0, %xmm1
; KNL-NEXT: vpextrq $1, %xmm1, %rax
-; KNL-NEXT: vcvtusi2sdq %rax, %xmm0, %xmm2
+; KNL-NEXT: vcvtusi2sdq %rax, %xmm2, %xmm2
; KNL-NEXT: vmovq %xmm1, %rax
-; KNL-NEXT: vcvtusi2sdq %rax, %xmm0, %xmm1
+; KNL-NEXT: vcvtusi2sdq %rax, %xmm3, %xmm1
; KNL-NEXT: vunpcklpd {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; KNL-NEXT: vextracti32x4 $2, %zmm0, %xmm2
; KNL-NEXT: vpextrq $1, %xmm2, %rax
-; KNL-NEXT: vcvtusi2sdq %rax, %xmm0, %xmm3
+; KNL-NEXT: vcvtusi2sdq %rax, %xmm3, %xmm3
; KNL-NEXT: vmovq %xmm2, %rax
-; KNL-NEXT: vcvtusi2sdq %rax, %xmm0, %xmm2
+; KNL-NEXT: vcvtusi2sdq %rax, %xmm4, %xmm2
; KNL-NEXT: vunpcklpd {{.*#+}} xmm2 = xmm2[0],xmm3[0]
; KNL-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1
; KNL-NEXT: vextracti32x4 $1, %zmm0, %xmm2
; KNL-NEXT: vpextrq $1, %xmm2, %rax
-; KNL-NEXT: vcvtusi2sdq %rax, %xmm0, %xmm3
+; KNL-NEXT: vcvtusi2sdq %rax, %xmm4, %xmm3
; KNL-NEXT: vmovq %xmm2, %rax
-; KNL-NEXT: vcvtusi2sdq %rax, %xmm0, %xmm2
+; KNL-NEXT: vcvtusi2sdq %rax, %xmm4, %xmm2
; KNL-NEXT: vunpcklpd {{.*#+}} xmm2 = xmm2[0],xmm3[0]
; KNL-NEXT: vpextrq $1, %xmm0, %rax
-; KNL-NEXT: vcvtusi2sdq %rax, %xmm0, %xmm3
+; KNL-NEXT: vcvtusi2sdq %rax, %xmm4, %xmm3
; KNL-NEXT: vmovq %xmm0, %rax
-; KNL-NEXT: vcvtusi2sdq %rax, %xmm0, %xmm0
+; KNL-NEXT: vcvtusi2sdq %rax, %xmm4, %xmm0
; KNL-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm3[0]
; KNL-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; KNL-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
Modified: llvm/trunk/test/CodeGen/X86/vec_int_to_fp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_int_to_fp.ll?rev=282356&r1=282355&r2=282356&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_int_to_fp.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_int_to_fp.ll Sun Sep 25 11:33:57 2016
@@ -418,9 +418,9 @@ define <2 x double> @uitofp_2i64_to_2f64
; AVX512-LABEL: uitofp_2i64_to_2f64:
; AVX512: # BB#0:
; AVX512-NEXT: vpextrq $1, %xmm0, %rax
-; AVX512-NEXT: vcvtusi2sdq %rax, %xmm0, %xmm1
+; AVX512-NEXT: vcvtusi2sdq %rax, %xmm1, %xmm1
; AVX512-NEXT: vmovq %xmm0, %rax
-; AVX512-NEXT: vcvtusi2sdq %rax, %xmm0, %xmm0
+; AVX512-NEXT: vcvtusi2sdq %rax, %xmm2, %xmm0
; AVX512-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX512-NEXT: retq
%cvt = uitofp <2 x i64> %a to <2 x double>
@@ -465,9 +465,9 @@ define <2 x double> @uitofp_2i32_to_2f64
; AVX512: # BB#0:
; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; AVX512-NEXT: vpextrq $1, %xmm0, %rax
-; AVX512-NEXT: vcvtusi2sdq %rax, %xmm0, %xmm1
+; AVX512-NEXT: vcvtusi2sdq %rax, %xmm1, %xmm1
; AVX512-NEXT: vmovq %xmm0, %rax
-; AVX512-NEXT: vcvtusi2sdq %rax, %xmm0, %xmm0
+; AVX512-NEXT: vcvtusi2sdq %rax, %xmm2, %xmm0
; AVX512-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX512-NEXT: retq
%shuf = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
@@ -717,14 +717,14 @@ define <4 x double> @uitofp_4i64_to_4f64
; AVX512: # BB#0:
; AVX512-NEXT: vextracti32x4 $1, %ymm0, %xmm1
; AVX512-NEXT: vpextrq $1, %xmm1, %rax
-; AVX512-NEXT: vcvtusi2sdq %rax, %xmm0, %xmm2
+; AVX512-NEXT: vcvtusi2sdq %rax, %xmm2, %xmm2
; AVX512-NEXT: vmovq %xmm1, %rax
-; AVX512-NEXT: vcvtusi2sdq %rax, %xmm0, %xmm1
+; AVX512-NEXT: vcvtusi2sdq %rax, %xmm3, %xmm1
; AVX512-NEXT: vunpcklpd {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; AVX512-NEXT: vpextrq $1, %xmm0, %rax
-; AVX512-NEXT: vcvtusi2sdq %rax, %xmm0, %xmm2
+; AVX512-NEXT: vcvtusi2sdq %rax, %xmm3, %xmm2
; AVX512-NEXT: vmovq %xmm0, %rax
-; AVX512-NEXT: vcvtusi2sdq %rax, %xmm0, %xmm0
+; AVX512-NEXT: vcvtusi2sdq %rax, %xmm3, %xmm0
; AVX512-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; AVX512-NEXT: vinsertf32x4 $1, %xmm1, %ymm0, %ymm0
; AVX512-NEXT: retq
@@ -1392,11 +1392,11 @@ define <4 x float> @uitofp_2i64_to_4f32(
; AVX512-LABEL: uitofp_2i64_to_4f32:
; AVX512: # BB#0:
; AVX512-NEXT: vpextrq $1, %xmm0, %rax
-; AVX512-NEXT: vcvtusi2ssq %rax, %xmm0, %xmm1
+; AVX512-NEXT: vcvtusi2ssq %rax, %xmm1, %xmm1
; AVX512-NEXT: vmovq %xmm0, %rax
-; AVX512-NEXT: vcvtusi2ssq %rax, %xmm0, %xmm0
+; AVX512-NEXT: vcvtusi2ssq %rax, %xmm2, %xmm0
; AVX512-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
-; AVX512-NEXT: vcvtusi2ssq %rax, %xmm0, %xmm1
+; AVX512-NEXT: vcvtusi2ssq %rax, %xmm2, %xmm1
; AVX512-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
; AVX512-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
; AVX512-NEXT: retq
@@ -1498,11 +1498,11 @@ define <4 x float> @uitofp_4i64_to_4f32_
; AVX512-LABEL: uitofp_4i64_to_4f32_undef:
; AVX512: # BB#0:
; AVX512-NEXT: vpextrq $1, %xmm0, %rax
-; AVX512-NEXT: vcvtusi2ssq %rax, %xmm0, %xmm1
+; AVX512-NEXT: vcvtusi2ssq %rax, %xmm1, %xmm1
; AVX512-NEXT: vmovq %xmm0, %rax
-; AVX512-NEXT: vcvtusi2ssq %rax, %xmm0, %xmm0
+; AVX512-NEXT: vcvtusi2ssq %rax, %xmm2, %xmm0
; AVX512-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
-; AVX512-NEXT: vcvtusi2ssq %rax, %xmm0, %xmm1
+; AVX512-NEXT: vcvtusi2ssq %rax, %xmm2, %xmm1
; AVX512-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
; AVX512-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
; AVX512-NEXT: retq
@@ -1872,16 +1872,16 @@ define <4 x float> @uitofp_4i64_to_4f32(
; AVX512-LABEL: uitofp_4i64_to_4f32:
; AVX512: # BB#0:
; AVX512-NEXT: vpextrq $1, %xmm0, %rax
-; AVX512-NEXT: vcvtusi2ssq %rax, %xmm0, %xmm1
+; AVX512-NEXT: vcvtusi2ssq %rax, %xmm1, %xmm1
; AVX512-NEXT: vmovq %xmm0, %rax
-; AVX512-NEXT: vcvtusi2ssq %rax, %xmm0, %xmm2
+; AVX512-NEXT: vcvtusi2ssq %rax, %xmm2, %xmm2
; AVX512-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3]
; AVX512-NEXT: vextracti32x4 $1, %ymm0, %xmm0
; AVX512-NEXT: vmovq %xmm0, %rax
-; AVX512-NEXT: vcvtusi2ssq %rax, %xmm0, %xmm2
+; AVX512-NEXT: vcvtusi2ssq %rax, %xmm3, %xmm2
; AVX512-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3]
; AVX512-NEXT: vpextrq $1, %xmm0, %rax
-; AVX512-NEXT: vcvtusi2ssq %rax, %xmm0, %xmm0
+; AVX512-NEXT: vcvtusi2ssq %rax, %xmm3, %xmm0
; AVX512-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX512-NEXT: retq
%cvt = uitofp <4 x i64> %a to <4 x float>
@@ -2340,9 +2340,9 @@ define <2 x double> @uitofp_load_2i64_to
; AVX512: # BB#0:
; AVX512-NEXT: vmovdqa64 (%rdi), %xmm0
; AVX512-NEXT: vpextrq $1, %xmm0, %rax
-; AVX512-NEXT: vcvtusi2sdq %rax, %xmm0, %xmm1
+; AVX512-NEXT: vcvtusi2sdq %rax, %xmm1, %xmm1
; AVX512-NEXT: vmovq %xmm0, %rax
-; AVX512-NEXT: vcvtusi2sdq %rax, %xmm0, %xmm0
+; AVX512-NEXT: vcvtusi2sdq %rax, %xmm2, %xmm0
; AVX512-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX512-NEXT: retq
%ld = load <2 x i64>, <2 x i64> *%a
@@ -2391,9 +2391,9 @@ define <2 x double> @uitofp_load_2i32_to
; AVX512-NEXT: vpxord %xmm1, %xmm1, %xmm1
; AVX512-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
; AVX512-NEXT: vpextrq $1, %xmm0, %rax
-; AVX512-NEXT: vcvtusi2sdq %rax, %xmm0, %xmm1
+; AVX512-NEXT: vcvtusi2sdq %rax, %xmm2, %xmm1
; AVX512-NEXT: vmovq %xmm0, %rax
-; AVX512-NEXT: vcvtusi2sdq %rax, %xmm0, %xmm0
+; AVX512-NEXT: vcvtusi2sdq %rax, %xmm2, %xmm0
; AVX512-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX512-NEXT: retq
%ld = load <2 x i32>, <2 x i32> *%a
@@ -2544,14 +2544,14 @@ define <4 x double> @uitofp_load_4i64_to
; AVX512-NEXT: vmovdqa64 (%rdi), %ymm0
; AVX512-NEXT: vextracti32x4 $1, %ymm0, %xmm1
; AVX512-NEXT: vpextrq $1, %xmm1, %rax
-; AVX512-NEXT: vcvtusi2sdq %rax, %xmm0, %xmm2
+; AVX512-NEXT: vcvtusi2sdq %rax, %xmm2, %xmm2
; AVX512-NEXT: vmovq %xmm1, %rax
-; AVX512-NEXT: vcvtusi2sdq %rax, %xmm0, %xmm1
+; AVX512-NEXT: vcvtusi2sdq %rax, %xmm3, %xmm1
; AVX512-NEXT: vunpcklpd {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; AVX512-NEXT: vpextrq $1, %xmm0, %rax
-; AVX512-NEXT: vcvtusi2sdq %rax, %xmm0, %xmm2
+; AVX512-NEXT: vcvtusi2sdq %rax, %xmm3, %xmm2
; AVX512-NEXT: vmovq %xmm0, %rax
-; AVX512-NEXT: vcvtusi2sdq %rax, %xmm0, %xmm0
+; AVX512-NEXT: vcvtusi2sdq %rax, %xmm3, %xmm0
; AVX512-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; AVX512-NEXT: vinsertf32x4 $1, %xmm1, %ymm0, %ymm0
; AVX512-NEXT: retq
@@ -3251,16 +3251,16 @@ define <4 x float> @uitofp_load_4i64_to_
; AVX512: # BB#0:
; AVX512-NEXT: vmovdqa64 (%rdi), %ymm0
; AVX512-NEXT: vpextrq $1, %xmm0, %rax
-; AVX512-NEXT: vcvtusi2ssq %rax, %xmm0, %xmm1
+; AVX512-NEXT: vcvtusi2ssq %rax, %xmm1, %xmm1
; AVX512-NEXT: vmovq %xmm0, %rax
-; AVX512-NEXT: vcvtusi2ssq %rax, %xmm0, %xmm2
+; AVX512-NEXT: vcvtusi2ssq %rax, %xmm2, %xmm2
; AVX512-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3]
; AVX512-NEXT: vextracti32x4 $1, %ymm0, %xmm0
; AVX512-NEXT: vmovq %xmm0, %rax
-; AVX512-NEXT: vcvtusi2ssq %rax, %xmm0, %xmm2
+; AVX512-NEXT: vcvtusi2ssq %rax, %xmm3, %xmm2
; AVX512-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3]
; AVX512-NEXT: vpextrq $1, %xmm0, %rax
-; AVX512-NEXT: vcvtusi2ssq %rax, %xmm0, %xmm0
+; AVX512-NEXT: vcvtusi2ssq %rax, %xmm3, %xmm0
; AVX512-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX512-NEXT: retq
%ld = load <4 x i64>, <4 x i64> *%a
@@ -3750,28 +3750,28 @@ define <8 x float> @uitofp_load_8i64_to_
; AVX512-NEXT: vmovdqa64 (%rdi), %zmm0
; AVX512-NEXT: vextracti32x4 $2, %zmm0, %xmm1
; AVX512-NEXT: vpextrq $1, %xmm1, %rax
-; AVX512-NEXT: vcvtusi2ssq %rax, %xmm0, %xmm2
+; AVX512-NEXT: vcvtusi2ssq %rax, %xmm2, %xmm2
; AVX512-NEXT: vmovq %xmm1, %rax
-; AVX512-NEXT: vcvtusi2ssq %rax, %xmm0, %xmm1
+; AVX512-NEXT: vcvtusi2ssq %rax, %xmm3, %xmm1
; AVX512-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[2,3]
; AVX512-NEXT: vextracti32x4 $3, %zmm0, %xmm2
; AVX512-NEXT: vmovq %xmm2, %rax
-; AVX512-NEXT: vcvtusi2ssq %rax, %xmm0, %xmm3
+; AVX512-NEXT: vcvtusi2ssq %rax, %xmm3, %xmm3
; AVX512-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm3[0],xmm1[3]
; AVX512-NEXT: vpextrq $1, %xmm2, %rax
-; AVX512-NEXT: vcvtusi2ssq %rax, %xmm0, %xmm2
+; AVX512-NEXT: vcvtusi2ssq %rax, %xmm4, %xmm2
; AVX512-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[0]
; AVX512-NEXT: vpextrq $1, %xmm0, %rax
-; AVX512-NEXT: vcvtusi2ssq %rax, %xmm0, %xmm2
+; AVX512-NEXT: vcvtusi2ssq %rax, %xmm4, %xmm2
; AVX512-NEXT: vmovq %xmm0, %rax
-; AVX512-NEXT: vcvtusi2ssq %rax, %xmm0, %xmm3
+; AVX512-NEXT: vcvtusi2ssq %rax, %xmm4, %xmm3
; AVX512-NEXT: vinsertps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[2,3]
; AVX512-NEXT: vextracti32x4 $1, %zmm0, %xmm0
; AVX512-NEXT: vmovq %xmm0, %rax
-; AVX512-NEXT: vcvtusi2ssq %rax, %xmm0, %xmm3
+; AVX512-NEXT: vcvtusi2ssq %rax, %xmm4, %xmm3
; AVX512-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm3[0],xmm2[3]
; AVX512-NEXT: vpextrq $1, %xmm0, %rax
-; AVX512-NEXT: vcvtusi2ssq %rax, %xmm0, %xmm0
+; AVX512-NEXT: vcvtusi2ssq %rax, %xmm4, %xmm0
; AVX512-NEXT: vinsertps {{.*#+}} xmm0 = xmm2[0,1,2],xmm0[0]
; AVX512-NEXT: vinsertf32x4 $1, %xmm1, %ymm0, %ymm0
; AVX512-NEXT: retq
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