[llvm] r282192 - [Hexagon] Remove USR_OVF from CtrRegs register class

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Thu Sep 22 15:59:41 2016
New Revision: 282192

URL: http://llvm.org/viewvc/llvm-project?rev=282192&view=rev
Log:
[Hexagon] Remove USR_OVF from CtrRegs register class

USR_OVF is a subregister of USR, which is a member of CtrRegs. Having both
a register and its proper subregister in the same register class has bad
consequences for lane mask calculation: based solely on the lane mask info,
USR_OVF would not appear to be a subregister of USR.

Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td

Modified: llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td?rev=282192&r1=282191&r2=282192&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td Thu Sep 22 15:59:41 2016
@@ -260,7 +260,10 @@ def CtrRegs : RegisterClass<"Hexagon", [
                             (add LC0, SA0, LC1, SA1,
                                  P3_0, C5,
                                  M0, M1, C6, C7, C8, CS0, CS1, UPCL, UPCH,
-                                 USR, USR_OVF, UGP, GP, PC)>;
+                                 USR, UGP, GP, PC)>;
+
+let isAllocatable = 0 in
+def UsrBits : RegisterClass<"Hexagon", [i1], 0, (add USR_OVF)>;
 
 let Size = 64, isAllocatable = 0 in
 def CtrRegs64 : RegisterClass<"Hexagon", [i64], 64,