[llvm] r282190 - [RDF] Use uint32_t for register numbers instead of unsigned

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Thu Sep 22 15:56:39 2016
New Revision: 282190

URL: http://llvm.org/viewvc/llvm-project?rev=282190&view=rev
Log:
[RDF] Use uint32_t for register numbers instead of unsigned

Modified:
    llvm/trunk/lib/Target/Hexagon/RDFGraph.cpp
    llvm/trunk/lib/Target/Hexagon/RDFGraph.h

Modified: llvm/trunk/lib/Target/Hexagon/RDFGraph.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/RDFGraph.cpp?rev=282190&r1=282189&r2=282190&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/RDFGraph.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/RDFGraph.cpp Thu Sep 22 15:56:39 2016
@@ -586,8 +586,8 @@ bool RegisterAliasInfo::covers(RegisterR
 
   assert(TargetRegisterInfo::isPhysicalRegister(RA.Reg) &&
          TargetRegisterInfo::isPhysicalRegister(RB.Reg));
-  unsigned A = RA.Sub != 0 ? TRI.getSubReg(RA.Reg, RA.Sub) : RA.Reg;
-  unsigned B = RB.Sub != 0 ? TRI.getSubReg(RB.Reg, RB.Sub) : RB.Reg;
+  uint32_t A = RA.Sub != 0 ? TRI.getSubReg(RA.Reg, RA.Sub) : RA.Reg;
+  uint32_t B = RB.Sub != 0 ? TRI.getSubReg(RB.Reg, RB.Sub) : RB.Reg;
   return TRI.isSubRegister(A, B);
 }
 
@@ -607,7 +607,7 @@ bool RegisterAliasInfo::covers(const Reg
   }
 
   // If any super-register of RR is present, then RR is covered.
-  unsigned Reg = RR.Sub == 0 ? RR.Reg : TRI.getSubReg(RR.Reg, RR.Sub);
+  uint32_t Reg = RR.Sub == 0 ? RR.Reg : TRI.getSubReg(RR.Reg, RR.Sub);
   for (MCSuperRegIterator SR(Reg, &TRI); SR.isValid(); ++SR)
     if (RRs.count({*SR, 0}))
       return true;
@@ -623,7 +623,7 @@ std::vector<RegisterRef> RegisterAliasIn
   if (TargetRegisterInfo::isVirtualRegister(RR.Reg))
     return AS;
   assert(TargetRegisterInfo::isPhysicalRegister(RR.Reg));
-  unsigned R = RR.Reg;
+  uint32_t R = RR.Reg;
   if (RR.Sub)
     R = TRI.getSubReg(RR.Reg, RR.Sub);
 
@@ -662,8 +662,8 @@ bool RegisterAliasInfo::alias(RegisterRe
 
   assert(PhysA && PhysB);
   (void)PhysA, (void)PhysB;
-  unsigned A = RA.Sub ? TRI.getSubReg(RA.Reg, RA.Sub) : RA.Reg;
-  unsigned B = RB.Sub ? TRI.getSubReg(RB.Reg, RB.Sub) : RB.Reg;
+  uint32_t A = RA.Sub ? TRI.getSubReg(RA.Reg, RA.Sub) : RA.Reg;
+  uint32_t B = RB.Sub ? TRI.getSubReg(RB.Reg, RB.Sub) : RB.Reg;
   for (MCRegAliasIterator I(A, &TRI, true); I.isValid(); ++I)
     if (B == *I)
       return true;
@@ -710,7 +710,7 @@ bool TargetOperandInfo::isFixedReg(const
   // uses or defs, and those lists do not allow sub-registers.
   if (Op.getSubReg() != 0)
     return false;
-  unsigned Reg = Op.getReg();
+  uint32_t Reg = Op.getReg();
   const MCPhysReg *ImpR = Op.isDef() ? D.getImplicitDefs()
                                      : D.getImplicitUses();
   if (!ImpR)

Modified: llvm/trunk/lib/Target/Hexagon/RDFGraph.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/RDFGraph.h?rev=282190&r1=282189&r2=282190&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/RDFGraph.h (original)
+++ llvm/trunk/lib/Target/Hexagon/RDFGraph.h Thu Sep 22 15:56:39 2016
@@ -384,7 +384,7 @@ namespace rdf {
   };
 
   struct RegisterRef {
-    unsigned Reg, Sub;
+    uint32_t Reg, Sub;
 
     // No non-trivial constructors, since this will be a member of a union.
     RegisterRef() = default;