[PATCH] D23172: IfConversion: Add implicit uses for live subregisters

[Quentin Colombet via llvm-commits]

Hi Matthias,

> On Sep 22, 2016, at 1:15 PM, Matthias Braun <matze at braunis.de> wrote:
> 
> MatzeB added a comment.
> 
> In https://reviews.llvm.org/D23172#550016, @qcolombet wrote:
> 
>>> If I understand correctly---the reg unit approach will still add the implicit operands, it will just use reg units to track liveness?
>> 
>> 
>> You shouldn't need the implicit operands anymore, because the double register would make the two reg unit of the simple register live and the uses would be from those reg unit.
>> In other words,
>> live in: D0 (sets reg unit A and B)
>> use S0 (uses reg unit A)
>> use S1 (uses reg unit B)
>> Would be valid without anything else. (Modulo updating the MachineVerifier to check at the RegUnit level).
>> But again, the problem with the RegUnit approach is that updating the live-ins may be expensive.
> 
> 
> I don't see how we could get away without the implicit operands in the if-conversion (without teaching many other parts of the compiler what predicated code is). I wrote a longer explanation in another review where I had to remind myself: https://reviews.llvm.org/D20907#476017

I was looking for your inputs regarding the representation of the live-in sets.
Sorry for the confusion, I guess you saw by then my clarification; we shouldn’t need this patch, the code we have for the implicit operand should just work.

Q.

> 
> 
> Repository:
>  rL LLVM
> 
> https://reviews.llvm.org/D23172
> 
> 
>