[PATCH] D24396: Target Power9 bit counting and vector comparison instructions through builtins (backend portion)

[Kit Barton via llvm-commits]

kbarton accepted this revision.
kbarton added a comment.
This revision is now accepted and ready to land.

Aside from a couple minor comments, this LGTM.


================
Comment at: lib/Target/PowerPC/PPCISelLowering.cpp:219
@@ -218,3 +218,3 @@
 
   // PowerPC does not have BSWAP, CTPOP or CTTZ
   setOperationAction(ISD::BSWAP, MVT::i32  , Expand);
----------------
Need to update this comment

================
Comment at: lib/Target/PowerPC/PPCISelLowering.cpp:7689
@@ +7688,3 @@
+      case Intrinsic::ppc_altivec_vcmpnezh_p: CompareOpc = 327; break;
+      case Intrinsic::ppc_altivec_vcmpnezw_p: CompareOpc = 391; break;
+      }
----------------
maybe want to add an llvm_unreachable for the default case.
I know this shouldn't happen right now, but it will prevent this from switch from getting out of sync with the outer case statements in the future. 

================
Comment at: lib/Target/PowerPC/PPCISelLowering.cpp:7770
@@ +7769,3 @@
+      case Intrinsic::ppc_altivec_vcmpnezh: CompareOpc = 327; break;
+      case Intrinsic::ppc_altivec_vcmpnezw: CompareOpc = 391; break;
+      }
----------------
And here


Repository:
  rL LLVM

https://reviews.llvm.org/D24396