[PATCH] D24556: [mips] Macro expansion for ld, sd for O32

[Vasileios Kalintiris via llvm-commits]

vkalintiris requested changes to this revision.
This revision now requires changes to proceed.

================
Comment at: lib/Target/Mips/AsmParser/MipsAsmParser.cpp:3899-3900
@@ +3898,4 @@
+
+  TOut.emitRRX(Opcode, FirstReg, BaseReg, FirstOffset, IDLoc, STI);
+  TOut.emitRRX(Opcode, SecondReg, BaseReg, SecondOffset, IDLoc, STI);
+
----------------
The GNU assembler orders these instructions in decreasing offsets when the source register is the same with the destination register.

================
Comment at: lib/Target/Mips/MipsInstrInfo.td:261-263
@@ -258,2 +260,5 @@
 }
+class ISA_MIPS1_NOT_MIPS3 {
+  list<Predicate> InsnPredicates = [NotMips3];
+}
 class ISA_MIPS32   { list<Predicate> InsnPredicates = [HasMips32]; }
----------------
We should group this with the `ISA_MIPS1_NOT_*` classes above.


Repository:
  rL LLVM

https://reviews.llvm.org/D24556