[llvm] r282131 - [RegisterBankInfo] Move to statically allocated RegisterBank.
Quentin Colombet via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 21 19:10:37 PDT 2016
Author: qcolombet
Date: Wed Sep 21 21:10:37 2016
New Revision: 282131
URL: http://llvm.org/viewvc/llvm-project?rev=282131&view=rev
Log:
[RegisterBankInfo] Move to statically allocated RegisterBank.
This commit is basically the first step toward what will
RegisterBankInfo look when it gets TableGen'ed.
It introduces a XXXGenRegisterBankInfo.def file that is what TableGen
will issue at some point. Moreover, the RegBanks field in
RegisterBankInfo changed to reflect the static (compile time) aspect of
the information.
Added:
llvm/trunk/lib/Target/AArch64/AArch64GenRegisterBankInfo.def
Modified:
llvm/trunk/include/llvm/CodeGen/GlobalISel/RegisterBank.h
llvm/trunk/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h
llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.h
Modified: llvm/trunk/include/llvm/CodeGen/GlobalISel/RegisterBank.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GlobalISel/RegisterBank.h?rev=282131&r1=282130&r2=282131&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/GlobalISel/RegisterBank.h (original)
+++ llvm/trunk/include/llvm/CodeGen/GlobalISel/RegisterBank.h Wed Sep 21 21:10:37 2016
@@ -37,15 +37,16 @@ private:
/// initialized yet.
static const unsigned InvalidID;
- /// Only the RegisterBankInfo can create RegisterBank.
+ /// Only the RegisterBankInfo can initialize RegisterBank properly.
+ friend RegisterBankInfo;
+
+public:
/// The default constructor will leave the object in
/// an invalid state. I.e. isValid() == false.
- /// The field must be updated to fix that.
+ /// The fields must be updated to fix that and only
+ /// RegisterBankInfo instances are allowed to do that
RegisterBank();
- friend RegisterBankInfo;
-
-public:
/// Get the identifier of this register bank.
unsigned getID() const { return ID; }
Modified: llvm/trunk/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h?rev=282131&r1=282130&r2=282131&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h (original)
+++ llvm/trunk/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h Wed Sep 21 21:10:37 2016
@@ -289,7 +289,7 @@ public:
protected:
/// Hold the set of supported register banks.
- std::unique_ptr<RegisterBank[]> RegBanks;
+ RegisterBank **RegBanks;
/// Total number of register banks.
unsigned NumRegBanks;
@@ -299,7 +299,7 @@ protected:
/// \note For the verify method to succeed all the \p NumRegBanks
/// must be initialized by createRegisterBank and updated with
/// addRegBankCoverage RegisterBank.
- RegisterBankInfo(unsigned NumRegBanks);
+ RegisterBankInfo(RegisterBank **RegBanks, unsigned NumRegBanks);
/// This constructor is meaningless.
/// It just provides a default constructor that can be used at link time
@@ -339,7 +339,7 @@ protected:
/// Get the register bank identified by \p ID.
RegisterBank &getRegBank(unsigned ID) {
assert(ID < getNumRegBanks() && "Accessing an unknown register bank");
- return RegBanks[ID];
+ return *RegBanks[ID];
}
/// Try to get the mapping of \p MI.
Modified: llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp?rev=282131&r1=282130&r2=282131&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp Wed Sep 21 21:10:37 2016
@@ -38,9 +38,14 @@ const unsigned RegisterBankInfo::Invalid
//------------------------------------------------------------------------------
// RegisterBankInfo implementation.
//------------------------------------------------------------------------------
-RegisterBankInfo::RegisterBankInfo(unsigned NumRegBanks)
- : NumRegBanks(NumRegBanks) {
- RegBanks.reset(new RegisterBank[NumRegBanks]);
+RegisterBankInfo::RegisterBankInfo(RegisterBank **RegBanks,
+ unsigned NumRegBanks)
+ : RegBanks(RegBanks), NumRegBanks(NumRegBanks) {
+ DEBUG(for (unsigned Idx = 0, End = getNumRegBanks(); Idx != End; ++Idx) {
+ assert(RegBanks[Idx] != nullptr && "Invalid RegisterBank");
+ assert(!RegBanks[Idx]->isValid() &&
+ "RegisterBank should be invalid before initialization");
+ });
}
bool RegisterBankInfo::verify(const TargetRegisterInfo &TRI) const {
Added: llvm/trunk/lib/Target/AArch64/AArch64GenRegisterBankInfo.def
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64GenRegisterBankInfo.def?rev=282131&view=auto
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64GenRegisterBankInfo.def (added)
+++ llvm/trunk/lib/Target/AArch64/AArch64GenRegisterBankInfo.def Wed Sep 21 21:10:37 2016
@@ -0,0 +1,28 @@
+//===- AArch64GenRegisterBankInfo.def ----------------------------*- C++ -*-==//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+/// \file
+/// This file defines all the static objects used by AArch64RegisterBankInfo.
+/// \todo This should be generated by TableGen.
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_BUILD_GLOBAL_ISEL
+#error "You shouldn't build this"
+#endif
+
+namespace llvm {
+namespace AArch64 {
+
+RegisterBank GPRRegBank;
+RegisterBank FPRRegBank;
+RegisterBank CCRRegBank;
+
+RegisterBank *RegBanks[] = {&GPRRegBank, &FPRRegBank, &CCRRegBank};
+
+} // End AArch64 namespace.
+} // End llvm namespace.
Modified: llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp?rev=282131&r1=282130&r2=282131&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp Wed Sep 21 21:10:37 2016
@@ -21,6 +21,9 @@
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
+// This file will be TableGen'ed at some point.
+#include "AArch64GenRegisterBankInfo.def"
+
using namespace llvm;
#ifndef LLVM_BUILD_GLOBAL_ISEL
@@ -28,7 +31,16 @@ using namespace llvm;
#endif
AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)
- : RegisterBankInfo(AArch64::NumRegisterBanks) {
+ : RegisterBankInfo(AArch64::RegBanks, AArch64::NumRegisterBanks) {
+ static bool AlreadyInit = false;
+ // We have only one set of register banks, whatever the subtarget
+ // is. Therefore, the initialization of the RegBanks table should be
+ // done only once. Indeed the table of all register banks
+ // (AArch64::RegBanks) is unique in the compiler. At some point, it
+ // will get tablegen'ed and the whole constructor becomes empty.
+ if (AlreadyInit)
+ return;
+ AlreadyInit = true;
// Initialize the GPR bank.
createRegisterBank(AArch64::GPRRegBankID, "GPR");
// The GPR register bank is fully defined by all the registers in
@@ -36,6 +48,8 @@ AArch64RegisterBankInfo::AArch64Register
addRegBankCoverage(AArch64::GPRRegBankID, AArch64::GPR64allRegClassID, TRI);
const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID);
(void)RBGPR;
+ assert(&AArch64::GPRRegBank == &RBGPR &&
+ "The order in RegBanks is messed up");
assert(RBGPR.covers(*TRI.getRegClass(AArch64::GPR32RegClassID)) &&
"Subclass not added?");
assert(RBGPR.getSize() == 64 && "GPRs should hold up to 64-bit");
@@ -47,6 +61,8 @@ AArch64RegisterBankInfo::AArch64Register
addRegBankCoverage(AArch64::FPRRegBankID, AArch64::QQQQRegClassID, TRI);
const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID);
(void)RBFPR;
+ assert(&AArch64::FPRRegBank == &RBFPR &&
+ "The order in RegBanks is messed up");
assert(RBFPR.covers(*TRI.getRegClass(AArch64::QQRegClassID)) &&
"Subclass not added?");
assert(RBFPR.covers(*TRI.getRegClass(AArch64::FPR64RegClassID)) &&
@@ -59,6 +75,8 @@ AArch64RegisterBankInfo::AArch64Register
addRegBankCoverage(AArch64::CCRRegBankID, AArch64::CCRRegClassID, TRI);
const RegisterBank &RBCCR = getRegBank(AArch64::CCRRegBankID);
(void)RBCCR;
+ assert(&AArch64::CCRRegBank == &RBCCR &&
+ "The order in RegBanks is messed up");
assert(RBCCR.covers(*TRI.getRegClass(AArch64::CCRRegClassID)) &&
"Class not added?");
assert(RBCCR.getSize() == 32 && "CCR should hold up to 32-bit");
Modified: llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.h?rev=282131&r1=282130&r2=282131&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.h (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.h Wed Sep 21 21:10:37 2016
@@ -27,6 +27,10 @@ enum {
CCRRegBankID = 2, /// Conditional register: NZCV.
NumRegisterBanks
};
+
+extern RegisterBank GPRRegBank;
+extern RegisterBank FPRRegBank;
+extern RegisterBank CCRRegBank;
} // End AArch64 namespace.
/// This class provides the information for the target register banks.
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