[PATCH] D24702: AArch64: Set shift bit of TLSLE HI12 add instruction

[Lei Liu via llvm-commits]

lliu0 updated this revision to Diff 72029.
lliu0 added a comment.

Fix AArch64 test breakage.

FAIL: LLVM::frameindices.ll
FAIL: LLVM::arm64-tls-modifiers-darwin.s
FAIL: LLVM::darwin-reloc-addsubimm.s


https://reviews.llvm.org/D24702

Files:
  lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp

Index: lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
===================================================================
--- lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
+++ lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
@@ -263,6 +263,14 @@
 
   ++MCNumFixups;
 
+  // Set the shift bit of the add instruction for relocation types
+  // R_AARCH64_TLSLE_ADD_TPREL_HI12 and R_AARCH64_TLSLD_ADD_DTPREL_HI12.
+  if (Expr->getKind() == MCExpr::Target) {
+    AArch64MCExpr::VariantKind RefKind = cast<AArch64MCExpr>(Expr)->getKind();
+    if (RefKind == AArch64MCExpr::VK_TPREL_HI12 ||
+        RefKind == AArch64MCExpr::VK_DTPREL_HI12)
+      ShiftVal = 12;
+  }
   return ShiftVal == 0 ? 0 : (1 << ShiftVal);
 }
 


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