[PATCH] D24702: AArch64: Set shift bit of TLSLE HI12 add instruction

[Lei Liu via llvm-commits]

lliu0 updated this revision to Diff 71898.
lliu0 added a comment.

Set shift bit for R_AARCH64_TLSLD_ADD_DTPREL_HI12 as well.
Added test case.


https://reviews.llvm.org/D24702

Files:
  lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
  test/MC/AArch64/tls-add-shift.s

Index: test/MC/AArch64/tls-add-shift.s
===================================================================
--- /dev/null
+++ test/MC/AArch64/tls-add-shift.s
@@ -0,0 +1,12 @@
+// RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj < %s -o - | \
+// RUN:   llvm-objdump -r -d - | FileCheck %s
+
+	// TLS add TPREL
+	add x2, x1, #:tprel_hi12:var
+// CHECK: add x2, x1, #0, lsl #12
+// CHECK-NEXT: R_AARCH64_TLSLE_ADD_TPREL_HI12 var
+
+	// TLS add DTPREL
+	add x4, x3, #:dtprel_hi12:var
+// CHECK: add x4, x3, #0, lsl #12
+// CHECK-NEXT: R_AARCH64_TLSLD_ADD_DTPREL_HI12 var
Index: lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
===================================================================
--- lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
+++ lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
@@ -263,6 +263,12 @@
 
   ++MCNumFixups;
 
+  // Set the shift bit of the add instruction for relocation types
+  // R_AARCH64_TLSLE_ADD_TPREL_HI12 and R_AARCH64_TLSLD_ADD_DTPREL_HI12.
+  AArch64MCExpr::VariantKind RefKind = cast<AArch64MCExpr>(Expr)->getKind();
+  if (RefKind == AArch64MCExpr::VK_TPREL_HI12 ||
+      RefKind == AArch64MCExpr::VK_DTPREL_HI12)
+    ShiftVal = 12;
   return ShiftVal == 0 ? 0 : (1 << ShiftVal);
 }
 


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