[llvm] r281896 - [AMDGPU] Fix s_branch with -1 offset
Sam Kolton via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 19 03:20:55 PDT 2016
Author: skolton
Date: Mon Sep 19 05:20:55 2016
New Revision: 281896
URL: http://llvm.org/viewvc/llvm-project?rev=281896&view=rev
Log:
[AMDGPU] Fix s_branch with -1 offset
Summary:
In case s_branch instruction target is itself backend should emit offset -1 but instead it emit 0.
'''
label:
s_branch label // should emit [0xff,0xff,0x82,0xbf]
'''
Tom, Matt: why are we adjusting fixup values in applyFixup() method instead of processFixup()? processFixup() is calling adjustFixupValue() but does nothing with its result.
Reviewers: vpykhtin, artem.tamazov, tstellarAMD
Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl
Differential Revision: https://reviews.llvm.org/D24671
Modified:
llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
llvm/trunk/test/MC/AMDGPU/labels-branch.s
Modified: llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp?rev=281896&r1=281895&r2=281896&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp Mon Sep 19 05:20:55 2016
@@ -133,24 +133,21 @@ void AMDGPUAsmBackend::processFixupValue
const MCValue &Target, uint64_t &Value,
bool &IsResolved) {
if (IsResolved)
- (void)adjustFixupValue(Fixup, Value, &Asm.getContext());
-
+ Value = adjustFixupValue(Fixup, Value, &Asm.getContext());
}
void AMDGPUAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
unsigned DataSize, uint64_t Value,
bool IsPCRel) const {
- unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
if (!Value)
return; // Doesn't change encoding.
- Value = adjustFixupValue(Fixup, Value, nullptr);
-
MCFixupKindInfo Info = getFixupKindInfo(Fixup.getKind());
// Shift the value into position.
Value <<= Info.TargetOffset;
+ unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
uint32_t Offset = Fixup.getOffset();
assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!");
Modified: llvm/trunk/test/MC/AMDGPU/labels-branch.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/labels-branch.s?rev=281896&r1=281895&r2=281896&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/labels-branch.s (original)
+++ llvm/trunk/test/MC/AMDGPU/labels-branch.s Mon Sep 19 05:20:55 2016
@@ -1,17 +1,24 @@
// RUN: llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s | FileCheck %s --check-prefix=VI
+// RUN: llvm-mc -arch=amdgcn -mcpu=fiji -filetype=obj %s | llvm-objdump -disassemble -mcpu=fiji - | FileCheck %s --check-prefix=BIN
loop_start:
s_branch loop_start
// VI: s_branch loop_start ; encoding: [A,A,0x82,0xbf]
// VI-NEXT: ; fixup A - offset: 0, value: loop_start, kind: fixup_si_sopp_br
+// BIN: loop_start:
+// BIN-NEXT: BF82FFFF
s_branch loop_end
// VI: s_branch loop_end ; encoding: [A,A,0x82,0xbf]
// VI-NEXT: ; fixup A - offset: 0, value: loop_end, kind: fixup_si_sopp_br
+// BIN: BF820000
+// BIN: loop_end:
loop_end:
s_branch gds
// VI: s_branch gds ; encoding: [A,A,0x82,0xbf]
// VI-NEXT: ; fixup A - offset: 0, value: gds, kind: fixup_si_sopp_br
+// BIN: BF820000
+// BIN: gds:
gds:
s_nop 0
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