[PATCH] D24702: AArch64: Set shift bit of TLSLE HI12 add instruction

[Lei Liu via llvm-commits]

lliu0 created this revision.
lliu0 added a reviewer: t.p.northover.
lliu0 added a subscriber: llvm-commits.
Herald added subscribers: rengolin, aemerson.

AArch64 LLVM assembler emits add instruction without shift bit to calculate the higher 12-bit address of TLS variables in local exec model.  This generates wrong code sequence to access TLS variables with thread offset larger than 0x1000.

https://reviews.llvm.org/D24702

Files:
  lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp

Index: lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
===================================================================
--- lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
+++ lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
@@ -263,6 +263,10 @@
 
   ++MCNumFixups;
 
+  // Set the shift bit of the add instruction for relocation type
+  // R_AARCH64_TLSLE_ADD_TPREL_HI12.
+  if (cast<AArch64MCExpr>(Expr)->getKind() == AArch64MCExpr::VK_TPREL_HI12)
+    return 0x1000;
   return 0;
 }
 


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D24702.71740.patch
Type: text/x-patch
Size: 517 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20160918/384a2ad6/attachment.bin>