[llvm] r281789 - AMDGPU/SI: Fix kernel argument ABI for HSA

Tom Stellard via llvm-commits llvm-commits at lists.llvm.org
Fri Sep 16 15:20:24 PDT 2016 

Author: tstellar
Date: Fri Sep 16 17:20:24 2016
New Revision: 281789

URL: http://llvm.org/viewvc/llvm-project?rev=281789&view=rev
Log:
AMDGPU/SI: Fix kernel argument ABI for HSA

Summary: i8, i16, and f16 values are not extended to 32-bit in the HSA kernel ABI.

Reviewers: arsenm

Subscribers: arsenm, kzhuravl, wdng, nhaehnle, llvm-commits, yaxunl

Differential Revision: https://reviews.llvm.org/D24621

Modified:
    llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
    llvm/trunk/test/CodeGen/AMDGPU/kernel-args.ll

Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp?rev=281789&r1=281788&r2=281789&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp Fri Sep 16 17:20:24 2016
@@ -660,7 +660,8 @@ void AMDGPUTargetLowering::analyzeFormal
 
     unsigned NumRegs = getNumRegisters(State.getContext(), In.ArgVT);
 
-    if (In.ArgVT == MVT::i16 || In.ArgVT == MVT::i8 || In.ArgVT == MVT::f16) {
+    if (!Subtarget->isAmdHsaOS() &&
+        (In.ArgVT == MVT::i16 || In.ArgVT == MVT::i8 || In.ArgVT == MVT::f16)) {
       // The ABI says the caller will extend these values to 32-bits.
       MemVT = In.ArgVT.isInteger() ? MVT::i32 : MVT::f32;
     } else if (NumRegs == 1) {

Modified: llvm/trunk/test/CodeGen/AMDGPU/kernel-args.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/kernel-args.ll?rev=281789&r1=281788&r2=281789&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/kernel-args.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/kernel-args.ll Fri Sep 16 17:20:24 2016
@@ -1,13 +1,20 @@
-; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck %s --check-prefix=SI --check-prefix=GCN --check-prefix=FUNC
-; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s --check-prefix=VI --check-prefix=GCN --check-prefix=FUNC
+; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck %s --check-prefixes=SI,GCN,MESA-GCN,FUNC
+; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s --check-prefixes=VI,GCN,MESA-VI,MESA-GCN,FUNC
+; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs | FileCheck %s --check-prefixes=VI,GCN,HSA-VI,FUNC
 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG --check-prefix=FUNC
 ; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=EG --check-prefix=FUNC
 
 ; FUNC-LABEL: {{^}}i8_arg:
 ; EG: AND_INT {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z
 ; SI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb
-; VI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x2c
-; GCN: s_and_b32 s{{[0-9]+}}, [[VAL]], 0xff
+; MESA-VI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x2c
+; MESA-GCN: s_and_b32 s{{[0-9]+}}, [[VAL]], 0xff
+; HSA-VI: s_add_u32 [[SPTR_LO:s[0-9]+]], s4, 8
+; HSA-VI: s_addc_u32 [[SPTR_HI:s[0-9]+]], s5, 0
+; HSA-VI: v_mov_b32_e32 v[[VPTR_LO:[0-9]+]], [[SPTR_LO]]
+; HSA-VI: v_mov_b32_e32 v[[VPTR_HI:[0-9]+]], [[SPTR_HI]]
+; FIXME: Should be using s_load_dword
+; HSA-VI: flat_load_ubyte v{{[0-9]+}}, v{{\[}}[[VPTR_LO]]:[[VPTR_HI]]]
 
 define void @i8_arg(i32 addrspace(1)* nocapture %out, i8 %in) nounwind {
 entry:
@@ -19,7 +26,13 @@ entry:
 ; FUNC-LABEL: {{^}}i8_zext_arg:
 ; EG: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z
 ; SI: s_load_dword s{{[0-9]}}, s[0:1], 0xb
-; VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c
+; MESA-VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c
+; HSA-VI: s_add_u32 [[SPTR_LO:s[0-9]+]], s4, 8
+; HSA-VI: s_addc_u32 [[SPTR_HI:s[0-9]+]], s5, 0
+; HSA-VI: v_mov_b32_e32 v[[VPTR_LO:[0-9]+]], [[SPTR_LO]]
+; HSA-VI: v_mov_b32_e32 v[[VPTR_HI:[0-9]+]], [[SPTR_HI]]
+; FIXME: Should be using s_load_dword
+; HSA-VI: flat_load_ubyte v{{[0-9]+}}, v{{\[}}[[VPTR_LO]]:[[VPTR_HI]]]
 
 define void @i8_zext_arg(i32 addrspace(1)* nocapture %out, i8 zeroext %in) nounwind {
 entry:
@@ -31,7 +44,13 @@ entry:
 ; FUNC-LABEL: {{^}}i8_sext_arg:
 ; EG: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z
 ; SI: s_load_dword s{{[0-9]}}, s[0:1], 0xb
-; VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c
+; MESA-VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c
+; HSA-VI: s_add_u32 [[SPTR_LO:s[0-9]+]], s4, 8
+; HSA-VI: s_addc_u32 [[SPTR_HI:s[0-9]+]], s5, 0
+; HSA-VI: v_mov_b32_e32 v[[VPTR_LO:[0-9]+]], [[SPTR_LO]]
+; HSA-VI: v_mov_b32_e32 v[[VPTR_HI:[0-9]+]], [[SPTR_HI]]
+; FIXME: Should be using s_load_dword
+; HSA-VI: flat_load_sbyte v{{[0-9]+}}, v{{\[}}[[VPTR_LO]]:[[VPTR_HI]]]
 
 define void @i8_sext_arg(i32 addrspace(1)* nocapture %out, i8 signext %in) nounwind {
 entry:
@@ -43,8 +62,14 @@ entry:
 ; FUNC-LABEL: {{^}}i16_arg:
 ; EG: AND_INT {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z
 ; SI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb
-; VI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x2c
-; GCN: s_and_b32 s{{[0-9]+}}, [[VAL]], 0xff
+; MESA-VI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x2c
+; MESA-GCN: s_and_b32 s{{[0-9]+}}, [[VAL]], 0xff
+; HSA-VI: s_add_u32 [[SPTR_LO:s[0-9]+]], s4, 8
+; HSA-VI: s_addc_u32 [[SPTR_HI:s[0-9]+]], s5, 0
+; HSA-VI: v_mov_b32_e32 v[[VPTR_LO:[0-9]+]], [[SPTR_LO]]
+; HSA-VI: v_mov_b32_e32 v[[VPTR_HI:[0-9]+]], [[SPTR_HI]]
+; FIXME: Should be using s_load_dword
+; HSA-VI: flat_load_ushort v{{[0-9]+}}, v{{\[}}[[VPTR_LO]]:[[VPTR_HI]]]
 
 define void @i16_arg(i32 addrspace(1)* nocapture %out, i16 %in) nounwind {
 entry:
@@ -56,7 +81,13 @@ entry:
 ; FUNC-LABEL: {{^}}i16_zext_arg:
 ; EG: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z
 ; SI: s_load_dword s{{[0-9]}}, s[0:1], 0xb
-; VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c
+; MESA-VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c
+; HSA-VI: s_add_u32 [[SPTR_LO:s[0-9]+]], s4, 8
+; HSA-VI: s_addc_u32 [[SPTR_HI:s[0-9]+]], s5, 0
+; HSA-VI: v_mov_b32_e32 v[[VPTR_LO:[0-9]+]], [[SPTR_LO]]
+; HSA-VI: v_mov_b32_e32 v[[VPTR_HI:[0-9]+]], [[SPTR_HI]]
+; FIXME: Should be using s_load_dword
+; HSA-VI: flat_load_ushort v{{[0-9]+}}, v{{\[}}[[VPTR_LO]]:[[VPTR_HI]]]
 
 define void @i16_zext_arg(i32 addrspace(1)* nocapture %out, i16 zeroext %in) nounwind {
 entry:
@@ -68,7 +99,13 @@ entry:
 ; FUNC-LABEL: {{^}}i16_sext_arg:
 ; EG: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z
 ; SI: s_load_dword s{{[0-9]}}, s[0:1], 0xb
-; VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c
+; MESA-VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c
+; HSA-VI: s_add_u32 [[SPTR_LO:s[0-9]+]], s4, 8
+; HSA-VI: s_addc_u32 [[SPTR_HI:s[0-9]+]], s5, 0
+; HSA-VI: v_mov_b32_e32 v[[VPTR_LO:[0-9]+]], [[SPTR_LO]]
+; HSA-VI: v_mov_b32_e32 v[[VPTR_HI:[0-9]+]], [[SPTR_HI]]
+; FIXME: Should be using s_load_dword
+; HSA-VI: flat_load_sshort v{{[0-9]+}}, v{{\[}}[[VPTR_LO]]:[[VPTR_HI]]]
 
 define void @i16_sext_arg(i32 addrspace(1)* nocapture %out, i16 signext %in) nounwind {
 entry:
@@ -80,7 +117,8 @@ entry:
 ; FUNC-LABEL: {{^}}i32_arg:
 ; EG: T{{[0-9]\.[XYZW]}}, KC0[2].Z
 ; SI: s_load_dword s{{[0-9]}}, s[0:1], 0xb
-; VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c
+; MESA-VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c
+; HSA-VI: s_load_dword s{{[0-9]}}, s[4:5], 0x8
 define void @i32_arg(i32 addrspace(1)* nocapture %out, i32 %in) nounwind {
 entry:
   store i32 %in, i32 addrspace(1)* %out, align 4
@@ -90,7 +128,8 @@ entry:
 ; FUNC-LABEL: {{^}}f32_arg:
 ; EG: T{{[0-9]\.[XYZW]}}, KC0[2].Z
 ; SI: s_load_dword s{{[0-9]}}, s[0:1], 0xb
-; VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c
+; MESA-VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c
+; HSA-VI: s_load_dword s{{[0-9]+}}, s[4:5], 0x8
 define void @f32_arg(float addrspace(1)* nocapture %out, float %in) nounwind {
 entry:
   store float %in, float addrspace(1)* %out, align 4
@@ -100,8 +139,10 @@ entry:
 ; FUNC-LABEL: {{^}}v2i8_arg:
 ; EG: VTX_READ_8
 ; EG: VTX_READ_8
-; GCN: buffer_load_ubyte
-; GCN: buffer_load_ubyte
+; MESA-GCN: buffer_load_ubyte
+; MESA-GCN: buffer_load_ubyte
+; HSA-VI: flat_load_ubyte
+; HSA-VI: flat_load_ubyte
 define void @v2i8_arg(<2 x i8> addrspace(1)* %out, <2 x i8> %in) {
 entry:
   store <2 x i8> %in, <2 x i8> addrspace(1)* %out
@@ -111,8 +152,10 @@ entry:
 ; FUNC-LABEL: {{^}}v2i16_arg:
 ; EG: VTX_READ_16
 ; EG: VTX_READ_16
-; GCN-DAG: buffer_load_ushort
-; GCN-DAG: buffer_load_ushort
+; MESA-GCN: buffer_load_ushort
+; MESA-GCN: buffer_load_ushort
+; HSA-VI: flat_load_ushort
+; HSA-VI: flat_load_ushort
 define void @v2i16_arg(<2 x i16> addrspace(1)* %out, <2 x i16> %in) {
 entry:
   store <2 x i16> %in, <2 x i16> addrspace(1)* %out
@@ -123,7 +166,8 @@ entry:
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].X
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[2].W
 ; SI: s_load_dwordx2 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xb
-; VI: s_load_dwordx2 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0x2c
+; MESA-VI: s_load_dwordx2 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0x2c
+; HSA-VI: s_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x8
 define void @v2i32_arg(<2 x i32> addrspace(1)* nocapture %out, <2 x i32> %in) nounwind {
 entry:
   store <2 x i32> %in, <2 x i32> addrspace(1)* %out, align 4
@@ -134,7 +178,8 @@ entry:
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].X
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[2].W
 ; SI: s_load_dwordx2 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xb
-; VI: s_load_dwordx2 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0x2c
+; MESA-VI: s_load_dwordx2 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0x2c
+; HSA-VI: s_load_dwordx2 s{{\[[0-9]:[0-9]\]}}, s[4:5], 0x8
 define void @v2f32_arg(<2 x float> addrspace(1)* nocapture %out, <2 x float> %in) nounwind {
 entry:
   store <2 x float> %in, <2 x float> addrspace(1)* %out, align 4
@@ -142,9 +187,15 @@ entry:
 }
 
 ; FUNC-LABEL: {{^}}v3i8_arg:
-; VTX_READ_8 T{{[0-9]}}.X, T{{[0-9]}}.X, 40
-; VTX_READ_8 T{{[0-9]}}.X, T{{[0-9]}}.X, 41
-; VTX_READ_8 T{{[0-9]}}.X, T{{[0-9]}}.X, 42
+; EG-DAG: VTX_READ_8 T{{[0-9]}}.X, T{{[0-9]}}.X, 40
+; EG-DAG: VTX_READ_8 T{{[0-9]}}.X, T{{[0-9]}}.X, 41
+; EG-DAG: VTX_READ_8 T{{[0-9]}}.X, T{{[0-9]}}.X, 42
+; MESA-GCN: buffer_load_ubyte
+; MESA-GCN: buffer_load_ubyte
+; MESA-GCN: buffer_load_ubyte
+; HSA-VI: flat_load_ubyte
+; HSA-VI: flat_load_ubyte
+; HSA-VI: flat_load_ubyte
 define void @v3i8_arg(<3 x i8> addrspace(1)* nocapture %out, <3 x i8> %in) nounwind {
 entry:
   store <3 x i8> %in, <3 x i8> addrspace(1)* %out, align 4
@@ -152,9 +203,15 @@ entry:
 }
 
 ; FUNC-LABEL: {{^}}v3i16_arg:
-; VTX_READ_16 T{{[0-9]}}.X, T{{[0-9]}}.X, 44
-; VTX_READ_16 T{{[0-9]}}.X, T{{[0-9]}}.X, 46
-; VTX_READ_16 T{{[0-9]}}.X, T{{[0-9]}}.X, 48
+; EG-DAG: VTX_READ_16 T{{[0-9]}}.X, T{{[0-9]}}.X, 44
+; EG-DAG: VTX_READ_16 T{{[0-9]}}.X, T{{[0-9]}}.X, 46
+; EG-DAG: VTX_READ_16 T{{[0-9]}}.X, T{{[0-9]}}.X, 48
+; MESA-GCN: buffer_load_ushort
+; MESA-GCN: buffer_load_ushort
+; MESA-GCN: buffer_load_ushort
+; HSA-VI: flat_load_ushort
+; HSA-VI: flat_load_ushort
+; HSA-VI: flat_load_ushort
 define void @v3i16_arg(<3 x i16> addrspace(1)* nocapture %out, <3 x i16> %in) nounwind {
 entry:
   store <3 x i16> %in, <3 x i16> addrspace(1)* %out, align 4
@@ -165,7 +222,8 @@ entry:
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W
 ; SI: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0xd
-; VI: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x34
+; MESA-VI: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x34
+; HSA-VI: s_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x10
 define void @v3i32_arg(<3 x i32> addrspace(1)* nocapture %out, <3 x i32> %in) nounwind {
 entry:
   store <3 x i32> %in, <3 x i32> addrspace(1)* %out, align 4
@@ -177,7 +235,8 @@ entry:
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W
 ; SI: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0xd
-; VI: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x34
+; MESA-VI: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x34
+; HSA-VI: s_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x10
 define void @v3f32_arg(<3 x float> addrspace(1)* nocapture %out, <3 x float> %in) nounwind {
 entry:
   store <3 x float> %in, <3 x float> addrspace(1)* %out, align 4
@@ -189,10 +248,14 @@ entry:
 ; EG: VTX_READ_8
 ; EG: VTX_READ_8
 ; EG: VTX_READ_8
-; GCN: buffer_load_ubyte
-; GCN: buffer_load_ubyte
-; GCN: buffer_load_ubyte
-; GCN: buffer_load_ubyte
+; MESA-GCN: buffer_load_ubyte
+; MESA-GCN: buffer_load_ubyte
+; MESA-GCN: buffer_load_ubyte
+; MESA-GCN: buffer_load_ubyte
+; HSA-VI: flat_load_ubyte
+; HSA-VI: flat_load_ubyte
+; HSA-VI: flat_load_ubyte
+; HSA-VI: flat_load_ubyte
 define void @v4i8_arg(<4 x i8> addrspace(1)* %out, <4 x i8> %in) {
 entry:
   store <4 x i8> %in, <4 x i8> addrspace(1)* %out
@@ -204,10 +267,14 @@ entry:
 ; EG: VTX_READ_16
 ; EG: VTX_READ_16
 ; EG: VTX_READ_16
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
+; MESA-GCN: buffer_load_ushort
+; MESA-GCN: buffer_load_ushort
+; MESA-GCN: buffer_load_ushort
+; MESA-GCN: buffer_load_ushort
+; HSA-GCN: flat_load_ushort
+; HSA-GCN: flat_load_ushort
+; HSA-GCN: flat_load_ushort
+; HSA-GCN: flat_load_ushort
 define void @v4i16_arg(<4 x i16> addrspace(1)* %out, <4 x i16> %in) {
 entry:
   store <4 x i16> %in, <4 x i16> addrspace(1)* %out
@@ -220,7 +287,8 @@ entry:
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].X
 ; SI: s_load_dwordx4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xd
-; VI: s_load_dwordx4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0x34
+; MESA-VI: s_load_dwordx4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0x34
+; HSA-VI: s_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x10
 define void @v4i32_arg(<4 x i32> addrspace(1)* nocapture %out, <4 x i32> %in) nounwind {
 entry:
   store <4 x i32> %in, <4 x i32> addrspace(1)* %out, align 4
@@ -233,7 +301,8 @@ entry:
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].X
 ; SI: s_load_dwordx4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xd
-; VI: s_load_dwordx4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0x34
+; MESA-VI: s_load_dwordx4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0x34
+; HSA-VI: s_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x10
 define void @v4f32_arg(<4 x float> addrspace(1)* nocapture %out, <4 x float> %in) nounwind {
 entry:
   store <4 x float> %in, <4 x float> addrspace(1)* %out, align 4
@@ -249,13 +318,21 @@ entry:
 ; EG: VTX_READ_8
 ; EG: VTX_READ_8
 ; EG: VTX_READ_8
-; GCN: buffer_load_ubyte
-; GCN: buffer_load_ubyte
-; GCN: buffer_load_ubyte
-; GCN: buffer_load_ubyte
-; GCN: buffer_load_ubyte
-; GCN: buffer_load_ubyte
-; GCN: buffer_load_ubyte
+; MESA-GCN: buffer_load_ubyte
+; MESA-GCN: buffer_load_ubyte
+; MESA-GCN: buffer_load_ubyte
+; MESA-GCN: buffer_load_ubyte
+; MESA-GCN: buffer_load_ubyte
+; MESA-GCN: buffer_load_ubyte
+; MESA-GCN: buffer_load_ubyte
+; HSA-GCN: float_load_ubyte
+; HSA-GCN: float_load_ubyte
+; HSA-GCN: float_load_ubyte
+; HSA-GCN: float_load_ubyte
+; HSA-GCN: float_load_ubyte
+; HSA-GCN: float_load_ubyte
+; HSA-GCN: float_load_ubyte
+; HSA-GCN: float_load_ubyte
 define void @v8i8_arg(<8 x i8> addrspace(1)* %out, <8 x i8> %in) {
 entry:
   store <8 x i8> %in, <8 x i8> addrspace(1)* %out
@@ -271,14 +348,22 @@ entry:
 ; EG: VTX_READ_16
 ; EG: VTX_READ_16
 ; EG: VTX_READ_16
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
+; MESA-GCN: buffer_load_ushort
+; MESA-GCN: buffer_load_ushort
+; MESA-GCN: buffer_load_ushort
+; MESA-GCN: buffer_load_ushort
+; MESA-GCN: buffer_load_ushort
+; MESA-GCN: buffer_load_ushort
+; MESA-GCN: buffer_load_ushort
+; MESA-GCN: buffer_load_ushort
+; HSA-VI: flat_load_ushort
+; HSA-VI: flat_load_ushort
+; HSA-VI: flat_load_ushort
+; HSA-VI: flat_load_ushort
+; HSA-VI: flat_load_ushort
+; HSA-VI: flat_load_ushort
+; HSA-VI: flat_load_ushort
+; HSA-VI: flat_load_ushort
 define void @v8i16_arg(<8 x i16> addrspace(1)* %out, <8 x i16> %in) {
 entry:
   store <8 x i16> %in, <8 x i16> addrspace(1)* %out
@@ -295,7 +380,8 @@ entry:
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].W
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].X
 ; SI: s_load_dwordx8 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x11
-; VI: s_load_dwordx8 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x44
+; MESA-VI: s_load_dwordx8 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x44
+; HSA-VI: s_load_dwordx8 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x20
 define void @v8i32_arg(<8 x i32> addrspace(1)* nocapture %out, <8 x i32> %in) nounwind {
 entry:
   store <8 x i32> %in, <8 x i32> addrspace(1)* %out, align 4
@@ -335,22 +421,38 @@ entry:
 ; EG: VTX_READ_8
 ; EG: VTX_READ_8
 ; EG: VTX_READ_8
-; GCN: buffer_load_ubyte
-; GCN: buffer_load_ubyte
-; GCN: buffer_load_ubyte
-; GCN: buffer_load_ubyte
-; GCN: buffer_load_ubyte
-; GCN: buffer_load_ubyte
-; GCN: buffer_load_ubyte
-; GCN: buffer_load_ubyte
-; GCN: buffer_load_ubyte
-; GCN: buffer_load_ubyte
-; GCN: buffer_load_ubyte
-; GCN: buffer_load_ubyte
-; GCN: buffer_load_ubyte
-; GCN: buffer_load_ubyte
-; GCN: buffer_load_ubyte
-; GCN: buffer_load_ubyte
+; MESA-GCN: buffer_load_ubyte
+; MESA-GCN: buffer_load_ubyte
+; MESA-GCN: buffer_load_ubyte
+; MESA-GCN: buffer_load_ubyte
+; MESA-GCN: buffer_load_ubyte
+; MESA-GCN: buffer_load_ubyte
+; MESA-GCN: buffer_load_ubyte
+; MESA-GCN: buffer_load_ubyte
+; MESA-GCN: buffer_load_ubyte
+; MESA-GCN: buffer_load_ubyte
+; MESA-GCN: buffer_load_ubyte
+; MESA-GCN: buffer_load_ubyte
+; MESA-GCN: buffer_load_ubyte
+; MESA-GCN: buffer_load_ubyte
+; MESA-GCN: buffer_load_ubyte
+; MESA-GCN: buffer_load_ubyte
+; HSA-VI: flat_load_ubyte
+; HSA-VI: flat_load_ubyte
+; HSA-VI: flat_load_ubyte
+; HSA-VI: flat_load_ubyte
+; HSA-VI: flat_load_ubyte
+; HSA-VI: flat_load_ubyte
+; HSA-VI: flat_load_ubyte
+; HSA-VI: flat_load_ubyte
+; HSA-VI: flat_load_ubyte
+; HSA-VI: flat_load_ubyte
+; HSA-VI: flat_load_ubyte
+; HSA-VI: flat_load_ubyte
+; HSA-VI: flat_load_ubyte
+; HSA-VI: flat_load_ubyte
+; HSA-VI: flat_load_ubyte
+; HSA-VI: flat_load_ubyte
 define void @v16i8_arg(<16 x i8> addrspace(1)* %out, <16 x i8> %in) {
 entry:
   store <16 x i8> %in, <16 x i8> addrspace(1)* %out
@@ -374,22 +476,38 @@ entry:
 ; EG: VTX_READ_16
 ; EG: VTX_READ_16
 ; EG: VTX_READ_16
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
+; MESA-GCN: buffer_load_ushort
+; MESA-GCN: buffer_load_ushort
+; MESA-GCN: buffer_load_ushort
+; MESA-GCN: buffer_load_ushort
+; MESA-GCN: buffer_load_ushort
+; MESA-GCN: buffer_load_ushort
+; MESA-GCN: buffer_load_ushort
+; MESA-GCN: buffer_load_ushort
+; MESA-GCN: buffer_load_ushort
+; MESA-GCN: buffer_load_ushort
+; MESA-GCN: buffer_load_ushort
+; MESA-GCN: buffer_load_ushort
+; MESA-GCN: buffer_load_ushort
+; MESA-GCN: buffer_load_ushort
+; MESA-GCN: buffer_load_ushort
+; MESA-GCN: buffer_load_ushort
+; HSA-VI: flat_load_ushort
+; HSA-VI: flat_load_ushort
+; HSA-VI: flat_load_ushort
+; HSA-VI: flat_load_ushort
+; HSA-VI: flat_load_ushort
+; HSA-VI: flat_load_ushort
+; HSA-VI: flat_load_ushort
+; HSA-VI: flat_load_ushort
+; HSA-VI: flat_load_ushort
+; HSA-VI: flat_load_ushort
+; HSA-VI: flat_load_ushort
+; HSA-VI: flat_load_ushort
+; HSA-VI: flat_load_ushort
+; HSA-VI: flat_load_ushort
+; HSA-VI: flat_load_ushort
+; HSA-VI: flat_load_ushort
 define void @v16i16_arg(<16 x i16> addrspace(1)* %out, <16 x i16> %in) {
 entry:
   store <16 x i16> %in, <16 x i16> addrspace(1)* %out
@@ -414,7 +532,8 @@ entry:
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].W
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[10].X
 ; SI: s_load_dwordx16 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x19
-; VI: s_load_dwordx16 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x64
+; MESA-VI: s_load_dwordx16 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x64
+; HSA-VI: s_load_dwordx16 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x40
 define void @v16i32_arg(<16 x i32> addrspace(1)* nocapture %out, <16 x i32> %in) nounwind {
 entry:
   store <16 x i32> %in, <16 x i32> addrspace(1)* %out, align 4
@@ -439,7 +558,8 @@ entry:
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].W
 ; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[10].X
 ; SI: s_load_dwordx16 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x19
-; VI: s_load_dwordx16 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x64
+; MESA-VI: s_load_dwordx16 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x64
+; HSA-VI: s_load_dwordx16 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x40
 define void @v16f32_arg(<16 x float> addrspace(1)* nocapture %out, <16 x float> %in) nounwind {
 entry:
   store <16 x float> %in, <16 x float> addrspace(1)* %out, align 4
@@ -447,9 +567,10 @@ entry:
 }
 
 ; FUNC-LABEL: {{^}}kernel_arg_i64:
-; GCN: s_load_dwordx2
-; GCN: s_load_dwordx2
-; GCN: buffer_store_dwordx2
+; MESA-GCN: s_load_dwordx2
+; MESA-GCN: s_load_dwordx2
+; MESA-GCN: buffer_store_dwordx2
+; HSA-VI: s_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x8
 define void @kernel_arg_i64(i64 addrspace(1)* %out, i64 %a) nounwind {
   store i64 %a, i64 addrspace(1)* %out, align 8
   ret void
@@ -458,9 +579,10 @@ define void @kernel_arg_i64(i64 addrspac
 ; FUNC-LABEL: {{^}}f64_kernel_arg:
 ; SI-DAG: s_load_dwordx2 s[{{[0-9]:[0-9]}}], s[0:1], 0x9
 ; SI-DAG: s_load_dwordx2 s[{{[0-9]:[0-9]}}], s[0:1], 0xb
-; VI-DAG: s_load_dwordx2 s[{{[0-9]:[0-9]}}], s[0:1], 0x24
-; VI-DAG: s_load_dwordx2 s[{{[0-9]:[0-9]}}], s[0:1], 0x2c
-; GCN: buffer_store_dwordx2
+; MESA-VI-DAG: s_load_dwordx2 s[{{[0-9]:[0-9]}}], s[0:1], 0x24
+; MESA-VI-DAG: s_load_dwordx2 s[{{[0-9]:[0-9]}}], s[0:1], 0x2c
+; MESA-GCN: buffer_store_dwordx2
+; HSA-VI: s_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x8
 define void @f64_kernel_arg(double addrspace(1)* %out, double  %in) {
 entry:
   store double %in, double addrspace(1)* %out

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