[PATCH] D24675: [AMDGPU] Stop using MCRegisterClass::getSize()

[Krzysztof Parzyszek via llvm-commits]

kparzysz added inline comments.

================
Comment at: lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp:231-233
@@ +230,5 @@
+// (move from MC* level to Target* level). Return size in bits.
+unsigned getRegBitWidth(const MCRegisterClass &RC) {
+  switch (RC.getID()) {
+  case AMDGPU::SCC_CLASSRegClassID:
+    return 1;
----------------
arsenm wrote:
> arsenm wrote:
> > arsenm wrote:
> > > I would prefer to add a new field in the register class than introducing more giant switches that need updates. Most of these register classes should be omitted also since only a handful are actually allocatable. VS_32RegClass for example is only used for operand constraints
> > Besides the unallocatable point, I guess this isn't so bad right now. I think we're going to need to do something different in these cases anyway to support 16-bit immediates in a 32-bit register class
> Oh, this is looking directly at the operand class. In that case, you can remove all of the R600_* classes, VReg_1,and TTMP*
Also removed SCC_CLASS. However I kept VS_32 and VS_64, even though they are not allocatable, because without VS_32 I had assertions in check-llvm.


Repository:
  rL LLVM

https://reviews.llvm.org/D24675