[PATCH] D24675: [AMDGPU] Stop using MCRegisterClass::getSize()

[Matt Arsenault via llvm-commits]

arsenm added inline comments.

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Comment at: lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp:217
@@ -216,3 +216,3 @@
     const MCOperand &Op = MI.getOperand(i);
-    if (getLitEncoding(Op, RC.getSize(), STI) != 255)
+    if (getLitEncoding(Op, AMDGPU::getRegBitWidth(RC)/8, STI) != 255)
       continue;
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Space around /

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Comment at: lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp:231-233
@@ +230,5 @@
+// (move from MC* level to Target* level). Return size in bits.
+unsigned getRegBitWidth(const MCRegisterClass &RC) {
+  switch (RC.getID()) {
+  case AMDGPU::SCC_CLASSRegClassID:
+    return 1;
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I would prefer to add a new field in the register class than introducing more giant switches that need updates. Most of these register classes should be omitted also since only a handful are actually allocatable. VS_32RegClass for example is only used for operand constraints


Repository:
  rL LLVM

https://reviews.llvm.org/D24675