[PATCH] D24631: [RFC] Implement variable-width register classes, step 1: API changes

[Krzysztof Parzyszek via llvm-commits]

kparzysz created this revision.
kparzysz added reviewers: theraven, t.p.northover, jyknight, jordy.potman.lists, reames, darthcloud, jleidel, simoncook, emaste, MatzeB, qcolombet.
kparzysz added a subscriber: llvm-commits.
kparzysz set the repository for this revision to rL LLVM.
Herald added a reviewer: tstellarAMD.
Herald added subscribers: nhaehnle, nemanjai, jyknight, arsenm, qcolombet, MatzeB, jholewinski.

Follow-up to the discussion in D23561: implementation of support for register classes with variable-sized registers.


Outline of the plan:

- Make register sizes, spill slot sizes and spill slot alignment be determined by feature bits from MCSubtargetInfo. At the moment, the AMD target uses the register size at that level, so this data must be available even without MachineFunction/TargetRegisterInfo/etc.
    
The register size and the spill slot size can actually be different (certain cases on Hexagon), and since there are cases where the intended meaning of the RC->getSize() is the register size (parts of the AMDGPU code) as well as cases where it is taken to be spill slot size (register allocation), the distinction between these two interpretations will be made explicit.

- The register size, spill slot size, and spill slot alignment will be acquired for a register class by functions from MCRegisterInfo, not from MCRegisterClass directly. These functions will also take MCSubtargetInfo as a parameter, to allow consultation with the feature bits.

- The actual format of the register class data as calculated by TableGen is not implemented in this step, and it will be done in the next step, together with the implementation of the .td syntax changes.

- This step is a NFC change to put new APIs in place. The rest of the changes should be isolated to the parts directly involved with processing the register class data, i.e. TableGen, MCRegisterInfo, and MCSubtargetInfo.  It should not be committed by itself, it serves to demonstrate this part of the proposed solution.


Repository:
  rL LLVM

https://reviews.llvm.org/D24631

Files:
  include/llvm/CodeGen/MachineRegisterInfo.h
  include/llvm/CodeGen/StackMaps.h
  include/llvm/MC/MCRegisterInfo.h
  include/llvm/Target/TargetLowering.h
  include/llvm/Target/TargetRegisterInfo.h
  lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp
  lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
  lib/CodeGen/AsmPrinter/DwarfDebug.cpp
  lib/CodeGen/AsmPrinter/DwarfExpression.cpp
  lib/CodeGen/AsmPrinter/DwarfExpression.h
  lib/CodeGen/AsmPrinter/DwarfUnit.cpp
  lib/CodeGen/DetectDeadLanes.cpp
  lib/CodeGen/MachineRegisterInfo.cpp
  lib/CodeGen/PeepholeOptimizer.cpp
  lib/CodeGen/PrologEpilogInserter.cpp
  lib/CodeGen/RegAllocFast.cpp
  lib/CodeGen/RegisterCoalescer.cpp
  lib/CodeGen/RegisterScavenging.cpp
  lib/CodeGen/StackMaps.cpp
  lib/CodeGen/TargetInstrInfo.cpp
  lib/CodeGen/TargetLoweringBase.cpp
  lib/CodeGen/TargetRegisterInfo.cpp
  lib/CodeGen/VirtRegMap.cpp
  lib/Target/AArch64/AArch64FrameLowering.cpp
  lib/Target/AArch64/AArch64ISelLowering.cpp
  lib/Target/AArch64/AArch64InstrInfo.cpp
  lib/Target/AMDGPU/AMDGPU.td
  lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
  lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
  lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp
  lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.h
  lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
  lib/Target/AMDGPU/R600ISelLowering.cpp
  lib/Target/AMDGPU/SIFixSGPRCopies.cpp
  lib/Target/AMDGPU/SIFoldOperands.cpp
  lib/Target/AMDGPU/SIFrameLowering.cpp
  lib/Target/AMDGPU/SIISelLowering.cpp
  lib/Target/AMDGPU/SIInsertWaits.cpp
  lib/Target/AMDGPU/SIInstrInfo.cpp
  lib/Target/AMDGPU/SIInstrInfo.h
  lib/Target/AMDGPU/SIInstrInfo.td
  lib/Target/AMDGPU/SIRegisterInfo.cpp
  lib/Target/AMDGPU/SIRegisterInfo.h
  lib/Target/AMDGPU/SIShrinkInstructions.cpp
  lib/Target/AMDGPU/SIWholeQuadMode.cpp
  lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
  lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
  lib/Target/ARM/ARMBaseInstrInfo.cpp
  lib/Target/ARM/ARMBaseRegisterInfo.cpp
  lib/Target/ARM/ARMFrameLowering.cpp
  lib/Target/ARM/ARMISelLowering.cpp
  lib/Target/ARM/ARMISelLowering.h
  lib/Target/BPF/BPFISelLowering.cpp
  lib/Target/Hexagon/BitTracker.cpp
  lib/Target/Hexagon/BitTracker.h
  lib/Target/Hexagon/HexagonBitSimplify.cpp
  lib/Target/Hexagon/HexagonBitTracker.cpp
  lib/Target/Hexagon/HexagonBitTracker.h
  lib/Target/Hexagon/HexagonExpandCondsets.cpp
  lib/Target/Hexagon/HexagonFrameLowering.cpp
  lib/Target/Hexagon/HexagonGenInsert.cpp
  lib/Target/Hexagon/HexagonISelLowering.cpp
  lib/Target/Hexagon/HexagonISelLowering.h
  lib/Target/Lanai/LanaiISelLowering.cpp
  lib/Target/MSP430/MSP430ISelLowering.cpp
  lib/Target/Mips/Mips16ISelLowering.cpp
  lib/Target/Mips/MipsAsmPrinter.cpp
  lib/Target/Mips/MipsFrameLowering.cpp
  lib/Target/Mips/MipsMachineFunction.cpp
  lib/Target/Mips/MipsSEFrameLowering.cpp
  lib/Target/Mips/MipsSEISelLowering.cpp
  lib/Target/Mips/MipsSEInstrInfo.cpp
  lib/Target/NVPTX/NVPTXISelLowering.cpp
  lib/Target/NVPTX/NVPTXInstrInfo.cpp
  lib/Target/PowerPC/PPCFrameLowering.cpp
  lib/Target/PowerPC/PPCISelLowering.cpp
  lib/Target/Sparc/SparcISelLowering.cpp
  lib/Target/SystemZ/SystemZISelLowering.cpp
  lib/Target/SystemZ/SystemZInstrInfo.cpp
  lib/Target/X86/X86FastISel.cpp
  lib/Target/X86/X86FrameLowering.cpp
  lib/Target/X86/X86ISelLowering.cpp
  lib/Target/X86/X86ISelLowering.h
  lib/Target/X86/X86InstrInfo.cpp
  lib/Target/X86/X86RegisterInfo.cpp
  lib/Target/XCore/XCoreFrameLowering.cpp
  lib/Target/XCore/XCoreISelLowering.cpp
  lib/Target/XCore/XCoreMachineFunctionInfo.cpp

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D24631.71556.patch
Type: text/x-patch
Size: 164316 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20160915/29055217/attachment-0001.bin>